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[AArch64][NFC] Use member variable RI instead getRegisterInfo in copyPhysReg (llvm#162826)
This patch uses the RI member variable directly in the member function AArch64InstrInfo::copyPhysReg, instead of redundant calls to the public API.
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 38 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -5064,17 +5064,15 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50645064
bool RenamableSrc) const {
50655065
if (AArch64::GPR32spRegClass.contains(DestReg) &&
50665066
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
5067-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5068-
50695067
if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
50705068
// If either operand is WSP, expand to ADD #0.
50715069
if (Subtarget.hasZeroCycleRegMoveGPR64() &&
50725070
!Subtarget.hasZeroCycleRegMoveGPR32()) {
50735071
// Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.
5074-
MCRegister DestRegX = TRI->getMatchingSuperReg(
5075-
DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
5076-
MCRegister SrcRegX = TRI->getMatchingSuperReg(
5077-
SrcReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
5072+
MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
5073+
&AArch64::GPR64spRegClass);
5074+
MCRegister SrcRegX = RI.getMatchingSuperReg(SrcReg, AArch64::sub_32,
5075+
&AArch64::GPR64spRegClass);
50785076
// This instruction is reading and writing X registers. This may upset
50795077
// the register scavenger and machine verifier, so we need to indicate
50805078
// that we are reading an undefined value from SrcRegX, but a proper
@@ -5097,14 +5095,14 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50975095
} else if (Subtarget.hasZeroCycleRegMoveGPR64() &&
50985096
!Subtarget.hasZeroCycleRegMoveGPR32()) {
50995097
// Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
5100-
MCRegister DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
5101-
&AArch64::GPR64spRegClass);
5098+
MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
5099+
&AArch64::GPR64spRegClass);
51025100
assert(DestRegX.isValid() && "Destination super-reg not valid");
51035101
MCRegister SrcRegX =
51045102
SrcReg == AArch64::WZR
51055103
? AArch64::XZR
5106-
: TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
5107-
&AArch64::GPR64spRegClass);
5104+
: RI.getMatchingSuperReg(SrcReg, AArch64::sub_32,
5105+
&AArch64::GPR64spRegClass);
51085106
assert(SrcRegX.isValid() && "Source super-reg not valid");
51095107
// This instruction is reading and writing X registers. This may upset
51105108
// the register scavenger and machine verifier, so we need to indicate
@@ -5334,11 +5332,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53345332
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
53355333
!Subtarget.hasZeroCycleRegMoveFPR64() &&
53365334
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
5337-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5338-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::dsub,
5339-
&AArch64::FPR128RegClass);
5340-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::dsub,
5341-
&AArch64::FPR128RegClass);
5335+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
5336+
&AArch64::FPR128RegClass);
5337+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
5338+
&AArch64::FPR128RegClass);
53425339
// This instruction is reading and writing Q registers. This may upset
53435340
// the register scavenger and machine verifier, so we need to indicate
53445341
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5359,11 +5356,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53595356
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
53605357
!Subtarget.hasZeroCycleRegMoveFPR64() &&
53615358
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
5362-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5363-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
5364-
&AArch64::FPR128RegClass);
5365-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
5366-
&AArch64::FPR128RegClass);
5359+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
5360+
&AArch64::FPR128RegClass);
5361+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
5362+
&AArch64::FPR128RegClass);
53675363
// This instruction is reading and writing Q registers. This may upset
53685364
// the register scavenger and machine verifier, so we need to indicate
53695365
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5374,11 +5370,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53745370
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
53755371
} else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
53765372
!Subtarget.hasZeroCycleRegMoveFPR32()) {
5377-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5378-
MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
5379-
&AArch64::FPR64RegClass);
5380-
MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
5381-
&AArch64::FPR64RegClass);
5373+
MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
5374+
&AArch64::FPR64RegClass);
5375+
MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
5376+
&AArch64::FPR64RegClass);
53825377
// This instruction is reading and writing D registers. This may upset
53835378
// the register scavenger and machine verifier, so we need to indicate
53845379
// that we are reading an undefined value from SrcRegD, but a proper
@@ -5398,11 +5393,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53985393
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
53995394
!Subtarget.hasZeroCycleRegMoveFPR64() &&
54005395
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
5401-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5402-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
5403-
&AArch64::FPR128RegClass);
5404-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
5405-
&AArch64::FPR128RegClass);
5396+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
5397+
&AArch64::FPR128RegClass);
5398+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
5399+
&AArch64::FPR128RegClass);
54065400
// This instruction is reading and writing Q registers. This may upset
54075401
// the register scavenger and machine verifier, so we need to indicate
54085402
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5413,11 +5407,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
54135407
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
54145408
} else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
54155409
!Subtarget.hasZeroCycleRegMoveFPR32()) {
5416-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5417-
MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
5418-
&AArch64::FPR64RegClass);
5419-
MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
5420-
&AArch64::FPR64RegClass);
5410+
MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
5411+
&AArch64::FPR64RegClass);
5412+
MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
5413+
&AArch64::FPR64RegClass);
54215414
// This instruction is reading and writing D registers. This may upset
54225415
// the register scavenger and machine verifier, so we need to indicate
54235416
// that we are reading an undefined value from SrcRegD, but a proper
@@ -5441,11 +5434,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
54415434
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
54425435
!Subtarget.hasZeroCycleRegMoveFPR64() &&
54435436
!Subtarget.hasZeroCycleRegMoveFPR64() && Subtarget.isNeonAvailable()) {
5444-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5445-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
5446-
&AArch64::FPR128RegClass);
5447-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
5448-
&AArch64::FPR128RegClass);
5437+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
5438+
&AArch64::FPR128RegClass);
5439+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
5440+
&AArch64::FPR128RegClass);
54495441
// This instruction is reading and writing Q registers. This may upset
54505442
// the register scavenger and machine verifier, so we need to indicate
54515443
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5456,11 +5448,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
54565448
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
54575449
} else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
54585450
!Subtarget.hasZeroCycleRegMoveFPR32()) {
5459-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5460-
MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
5461-
&AArch64::FPR64RegClass);
5462-
MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
5463-
&AArch64::FPR64RegClass);
5451+
MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
5452+
&AArch64::FPR64RegClass);
5453+
MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
5454+
&AArch64::FPR64RegClass);
54645455
// This instruction is reading and writing D registers. This may upset
54655456
// the register scavenger and machine verifier, so we need to indicate
54665457
// that we are reading an undefined value from SrcRegD, but a proper
@@ -5532,9 +5523,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
55325523
}
55335524

55345525
#ifndef NDEBUG
5535-
const TargetRegisterInfo &TRI = getRegisterInfo();
5536-
errs() << TRI.getRegAsmName(DestReg) << " = COPY "
5537-
<< TRI.getRegAsmName(SrcReg) << "\n";
5526+
errs() << RI.getRegAsmName(DestReg) << " = COPY " << RI.getRegAsmName(SrcReg)
5527+
<< "\n";
55385528
#endif
55395529
llvm_unreachable("unimplemented reg-to-reg copy");
55405530
}

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