[LLVM] Port SVE tests in llvm/test/CodeGen/AArch64 to use splat()

This is preparation work towards making such splats use Constant{Int,FP}
by default for scalable vectors.

Author: paulwalker-arm

llvm/test/CodeGen/AArch64/DAGCombine_vscale.ll

@@ -10,10 +10,8 @@ define <vscale x 4 x i32> @sext_inreg(<vscale x 4 x i32> %a) {
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    sxth z0.s, p0/m, z0.s
 ; CHECK-NEXT:    ret
-  %in = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
-  %splat = shufflevector <vscale x 4 x i32> %in, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
-  %sext = shl <vscale x 4 x i32> %a, %splat
-  %conv = ashr <vscale x 4 x i32> %sext, %splat
+  %sext = shl <vscale x 4 x i32> %a, splat(i32 16)
+  %conv = ashr <vscale x 4 x i32> %sext, splat(i32 16)
   ret <vscale x 4 x i32> %conv
 }
 
@@ -23,12 +21,8 @@ define <vscale x 4 x i32> @ashr_shl(<vscale x 4 x i32> %a)  {
 ; CHECK-NEXT:    lsl z0.s, z0.s, #8
 ; CHECK-NEXT:    asr z0.s, z0.s, #16
 ; CHECK-NEXT:    ret
-  %in1 = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
-  %splat1 = shufflevector <vscale x 4 x i32> %in1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
-  %in2 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
-  %splat2 = shufflevector <vscale x 4 x i32> %in2, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
-  %shl = shl <vscale x 4 x i32> %a, %splat1
-  %r = ashr <vscale x 4 x i32> %shl, %splat2
+  %shl = shl <vscale x 4 x i32> %a, splat(i32 8)
+  %r = ashr <vscale x 4 x i32> %shl, splat(i32 16)
   ret <vscale x 4 x i32> %r
 }
 
@@ -38,12 +32,8 @@ define <vscale x 4 x i32> @ashr_shl_illegal_trunc_vec_ty(<vscale x 4 x i32> %a)
 ; CHECK-NEXT:    lsl z0.s, z0.s, #8
 ; CHECK-NEXT:    asr z0.s, z0.s, #11
 ; CHECK-NEXT:    ret
-  %in1 = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
-  %splat1 = shufflevector <vscale x 4 x i32> %in1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
-  %in2 = insertelement <vscale x 4 x i32> undef, i32 11, i32 0
-  %splat2 = shufflevector <vscale x 4 x i32> %in2, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
-  %shl = shl <vscale x 4 x i32> %a, %splat1
-  %r = ashr <vscale x 4 x i32> %shl, %splat2
+  %shl = shl <vscale x 4 x i32> %a, splat(i32 8)
+  %r = ashr <vscale x 4 x i32> %shl, splat(i32 11)
   ret <vscale x 4 x i32> %r
 }
 
@@ -55,12 +45,8 @@ define <vscale x 4 x i32> @ashr_add_shl_nxv4i8(<vscale x 4 x i32> %a) {
 ; CHECK-NEXT:    add z0.s, z0.s, z1.s
 ; CHECK-NEXT:    asr z0.s, z0.s, #24
 ; CHECK-NEXT:    ret
-  %in1 = insertelement <vscale x 4 x i32> undef, i32 24, i32 0
-  %splat1 = shufflevector <vscale x 4 x i32> %in1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
-  %in2 = insertelement <vscale x 4 x i32> undef, i32 16777216, i32 0
-  %splat2 = shufflevector <vscale x 4 x i32> %in2, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
-  %conv = shl <vscale x 4 x i32> %a, %splat1
-  %sext = add <vscale x 4 x i32> %conv, %splat2
-  %conv1 = ashr <vscale x 4 x i32> %sext, %splat1
+  %conv = shl <vscale x 4 x i32> %a, splat(i32 24)
+  %sext = add <vscale x 4 x i32> %conv, splat(i32 16777216)
+  %conv1 = ashr <vscale x 4 x i32> %sext, splat(i32 24)
   ret <vscale x 4 x i32> %conv1
 }

llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll

@@ -1165,9 +1165,7 @@ define <vscale x 2 x i64> @fshl_rot_const_i64(<vscale x 2 x i64> %a){
 ; CHECK-NEXT:    lsl z0.d, z0.d, #3
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    ret
-  %insert = insertelement <vscale x 2 x i64> poison, i64 3, i32 0
-  %shuf = shufflevector <vscale x 2 x i64> %insert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
-  %fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %shuf)
+  %fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 3))
   ret <vscale x 2 x i64> %fshl
 }
 

llvm/test/CodeGen/AArch64/sme-disable-rematerialize-with-streaming-mode-changes.ll

@@ -54,9 +54,7 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %index.03 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   call void asm sideeffect "", "~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27}"() nounwind
-  %ptrue.ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0
-  %ptrue = shufflevector <vscale x 16 x i1> %ptrue.ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
-  call void @bar(<vscale x 16 x i1> %ptrue)
+  call void @bar(<vscale x 16 x i1> splat(i1 true))
   %inc = add nuw nsw i32 %index.03, 1
   %exitcond.not = icmp eq i32 %inc, %N
   br i1 %exitcond.not, label %for.cond.cleanup, label %for.body

llvm/test/CodeGen/AArch64/sve-adr.ll

@@ -14,10 +14,8 @@ define <vscale x 4 x i32>  @adr_32bit_lsl1(<vscale x 4 x i32>  %base, <vscale x
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adr z0.s, [z0.s, z1.s, lsl #1]
 ; CHECK-NEXT:    ret
-  %splat_insert = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
-  %one = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
-  %shiftedOffset = shl <vscale x 4 x i32> %idx, %one
-  %address = add <vscale x 4 x i32> %base, %shiftedOffset
+  %offset = shl <vscale x 4 x i32> %idx, splat (i32 1)
+  %address = add <vscale x 4 x i32> %base, %offset
   ret <vscale x 4 x i32>  %address
 }
 
@@ -26,10 +24,8 @@ define <vscale x 4 x i32>  @adr_32bit_lsl2(<vscale x 4 x i32>  %base, <vscale x
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adr z0.s, [z0.s, z1.s, lsl #2]
 ; CHECK-NEXT:    ret
-  %splat_insert = insertelement <vscale x 4 x i32> poison, i32 2, i32 0
-  %two = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
-  %shiftedOffset = shl <vscale x 4 x i32> %idx, %two
-  %address = add <vscale x 4 x i32> %base, %shiftedOffset
+  %offset = shl <vscale x 4 x i32> %idx, splat (i32 2)
+  %address = add <vscale x 4 x i32> %base, %offset
   ret <vscale x 4 x i32>  %address
 }
 
@@ -38,10 +34,8 @@ define <vscale x 4 x i32>  @adr_32bit_lsl3(<vscale x 4 x i32>  %base, <vscale x
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adr z0.s, [z0.s, z1.s, lsl #3]
 ; CHECK-NEXT:    ret
-  %splat_insert = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
-  %three = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
-  %shiftedOffset = shl <vscale x 4 x i32> %idx, %three
-  %address = add <vscale x 4 x i32> %base, %shiftedOffset
+  %offset = shl <vscale x 4 x i32> %idx, splat (i32 3)
+  %address = add <vscale x 4 x i32> %base, %offset
   ret <vscale x 4 x i32>  %address
 }
 

llvm/test/CodeGen/AArch64/sve-cmp-folds.ll

@@ -8,9 +8,7 @@ define <vscale x 8 x i1> @not_icmp_sle_nxv8i16(<vscale x 8 x i16> %a, <vscale x
 ; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, z1.h
 ; CHECK-NEXT:    ret
   %icmp = icmp sle <vscale x 8 x i16> %a, %b
-  %tmp = insertelement <vscale x 8 x i1> undef, i1 true, i32 0
-  %ones = shufflevector <vscale x 8 x i1> %tmp, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
-  %not = xor <vscale x 8 x i1> %ones, %icmp
+  %not = xor <vscale x 8 x i1> splat(i1 true), %icmp
   ret <vscale x 8 x i1> %not
 }
 
@@ -21,9 +19,7 @@ define <vscale x 4 x i1> @not_icmp_sgt_nxv4i32(<vscale x 4 x i32> %a, <vscale x
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, z0.s
 ; CHECK-NEXT:    ret
   %icmp = icmp sgt <vscale x 4 x i32> %a, %b
-  %tmp = insertelement <vscale x 4 x i1> undef, i1 true, i32 0
-  %ones = shufflevector <vscale x 4 x i1> %tmp, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
-  %not = xor <vscale x 4 x i1> %icmp, %ones
+  %not = xor <vscale x 4 x i1> %icmp, splat(i1 true)
   ret <vscale x 4 x i1> %not
 }
 
@@ -34,9 +30,7 @@ define <vscale x 2 x i1> @not_fcmp_une_nxv2f64(<vscale x 2 x double> %a, <vscale
 ; CHECK-NEXT:    fcmeq p0.d, p0/z, z0.d, z1.d
 ; CHECK-NEXT:    ret
   %icmp = fcmp une <vscale x 2 x double> %a, %b
-  %tmp = insertelement <vscale x 2 x i1> undef, i1 true, i32 0
-  %ones = shufflevector <vscale x 2 x i1> %tmp, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
-  %not = xor <vscale x 2 x i1> %icmp, %ones
+  %not = xor <vscale x 2 x i1> %icmp, splat(i1 true)
   ret <vscale x 2 x i1> %not
 }
 
@@ -47,9 +41,7 @@ define <vscale x 4 x i1> @not_fcmp_uge_nxv4f32(<vscale x 4 x float> %a, <vscale
 ; CHECK-NEXT:    fcmgt p0.s, p0/z, z1.s, z0.s
 ; CHECK-NEXT:    ret
   %icmp = fcmp uge <vscale x 4 x float> %a, %b
-  %tmp = insertelement <vscale x 4 x i1> undef, i1 true, i32 0
-  %ones = shufflevector <vscale x 4 x i1> %tmp, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
-  %not = xor <vscale x 4 x i1> %icmp, %ones
+  %not = xor <vscale x 4 x i1> %icmp, splat(i1 true)
   ret <vscale x 4 x i1> %not
 }
 

llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll

@@ -17,10 +17,8 @@ define void @dead_masked_store_alltrue_same(<vscale x 4 x i32> %val, ptr %a, <vs
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
 ; CHECK-NEXT:    ret
-  %alltrue.ins = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
-  %alltrue = shufflevector  <vscale x 4 x i1> %alltrue.ins,  <vscale x 4 x i1> poison,  <vscale x 4 x i32> zeroinitializer
   call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
-  call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %alltrue)
+  call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> splat(i1 true))
   ret void
 }
 
@@ -30,10 +28,8 @@ define void @dead_masked_store_alltrue_bigger(<vscale x 4 x i16> %val, <vscale x
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    st1w { z1.s }, p0, [x0]
 ; CHECK-NEXT:    ret
-  %alltrue.ins = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
-  %alltrue = shufflevector  <vscale x 4 x i1> %alltrue.ins,  <vscale x 4 x i1> poison,  <vscale x 4 x i32> zeroinitializer
   call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
-  call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val1, ptr %a, i32 4, <vscale x 4 x i1> %alltrue)
+  call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val1, ptr %a, i32 4, <vscale x 4 x i1> splat(i1 true))
   ret void
 }
 
@@ -44,10 +40,8 @@ define void @dead_masked_store_alltrue_smaller(<vscale x 4 x i32> %val, <vscale
 ; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
 ; CHECK-NEXT:    st1h { z1.s }, p1, [x0]
 ; CHECK-NEXT:    ret
-  %alltrue.ins = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
-  %alltrue = shufflevector  <vscale x 4 x i1> %alltrue.ins,  <vscale x 4 x i1> poison,  <vscale x 4 x i32> zeroinitializer
   call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
-  call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %val1, ptr %a, i32 4, <vscale x 4 x i1> %alltrue)
+  call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %val1, ptr %a, i32 4, <vscale x 4 x i1> splat(i1 true))
   ret void
 }
 

llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll

@@ -392,9 +392,7 @@ define <2 x float> @extract_v2f32_nxv4f32_splat_const() {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmov v0.2s, #1.00000000
 ; CHECK-NEXT:    ret
-  %ins = insertelement <vscale x 4 x float> poison, float 1.0, i32 0
-  %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
-  %ext = call <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
+  %ext = call <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> splat(float 1.0), i64 0)
   ret <2 x float> %ext
 }
 
@@ -403,9 +401,7 @@ define <4 x i32> @extract_v4i32_nxv8i32_splat_const() {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v0.4s, #1
 ; CHECK-NEXT:    ret
-  %ins = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
-  %splat = shufflevector <vscale x 8 x i32> %ins, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
-  %ext = call <4 x i32> @llvm.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32> %splat, i64 0)
+  %ext = call <4 x i32> @llvm.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32> splat(i32 1), i64 0)
   ret <4 x i32> %ext
 }
 

llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll

@@ -1039,9 +1039,7 @@ define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat_const() {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmov z0.s, #1.00000000
 ; CHECK-NEXT:    ret
-  %ins = insertelement <vscale x 4 x float> poison, float 1.0, i32 0
-  %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
-  %ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
+  %ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> splat(float 1.0), i64 0)
   ret <vscale x 2 x float> %ext
 }
 
@@ -1050,9 +1048,7 @@ define <vscale x 4 x i32> @extract_nxv4i32_nxv8i32_splat_const() {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.s, #1 // =0x1
 ; CHECK-NEXT:    ret
-  %ins = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
-  %splat = shufflevector <vscale x 8 x i32> %ins, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
-  %ext = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %splat, i64 0)
+  %ext = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> splat(i32 1), i64 0)
   ret <vscale x 4 x i32> %ext
 }
 
@@ -1061,9 +1057,7 @@ define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_ones() {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    ret
-  %ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0
-  %splat = shufflevector <vscale x 16 x i1> %ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
-  %ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %splat, i64 0)
+  %ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> splat(i1 true), i64 0)
   ret <vscale x 2 x i1> %ext
 }
 

llvm/test/CodeGen/AArch64/sve-fadda-select.ll

@@ -10,9 +10,7 @@ define float @pred_fadda_nxv2f32(float %x, <vscale x 2 x float> %y, <vscale x 2
 ; CHECK-NEXT:    fadda s0, p0, s0, z1.s
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
 ; CHECK-NEXT:    ret
-  %i = insertelement <vscale x 2 x float> poison, float -0.000000e+00, i32 0
-  %minus0 = shufflevector <vscale x 2 x float> %i, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
-  %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x float> %y, <vscale x 2 x float> %minus0
+  %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x float> %y, <vscale x 2 x float> splat(float -0.000000e+00)
   %fadda = call float @llvm.vector.reduce.fadd.nxv2f32(float %x, <vscale x 2 x float> %sel)
   ret float %fadda
 }
@@ -24,9 +22,7 @@ define float @pred_fadda_nxv4f32(float %x, <vscale x 4 x float> %y, <vscale x 4
 ; CHECK-NEXT:    fadda s0, p0, s0, z1.s
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
 ; CHECK-NEXT:    ret
-  %i = insertelement <vscale x 4 x float> poison, float -0.000000e+00, i32 0
-  %minus0 = shufflevector <vscale x 4 x float> %i, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
-  %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x float> %y, <vscale x 4 x float> %minus0
+  %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x float> %y, <vscale x 4 x float> splat(float -0.000000e+00)
   %fadda = call float @llvm.vector.reduce.fadd.nxv4f32(float %x, <vscale x 4 x float> %sel)
   ret float %fadda
 }
@@ -38,9 +34,7 @@ define double @pred_fadda_nxv2f64(double %x, <vscale x 2 x double> %y, <vscale x
 ; CHECK-NEXT:    fadda d0, p0, d0, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
-  %i = insertelement <vscale x 2 x double> poison, double -0.000000e+00, i32 0
-  %minus0 = shufflevector <vscale x 2 x double> %i, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
-  %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x double> %y, <vscale x 2 x double> %minus0
+  %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x double> %y, <vscale x 2 x double> splat(double -0.000000e+00)
   %fadda = call double @llvm.vector.reduce.fadd.nxv2f64(double %x, <vscale x 2 x double> %sel)
   ret double %fadda
 }
@@ -52,9 +46,7 @@ define half @pred_fadda_nxv2f16(half %x, <vscale x 2 x half> %y, <vscale x 2 x i
 ; CHECK-NEXT:    fadda h0, p0, h0, z1.h
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
 ; CHECK-NEXT:    ret
-  %i = insertelement <vscale x 2 x half> poison, half -0.000000e+00, i32 0
-  %minus0 = shufflevector <vscale x 2 x half> %i, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
-  %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x half> %y, <vscale x 2 x half> %minus0
+  %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x half> %y, <vscale x 2 x half> splat(half -0.000000e+00)
   %fadda = call half @llvm.vector.reduce.fadd.nxv2f16(half %x, <vscale x 2 x half> %sel)
   ret half %fadda
 }
@@ -66,9 +58,7 @@ define half @pred_fadda_nxv4f16(half %x, <vscale x 4 x half> %y, <vscale x 4 x i
 ; CHECK-NEXT:    fadda h0, p0, h0, z1.h
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
 ; CHECK-NEXT:    ret
-  %i = insertelement <vscale x 4 x half> poison, half -0.000000e+00, i32 0
-  %minus0 = shufflevector <vscale x 4 x half> %i, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
-  %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x half> %y, <vscale x 4 x half> %minus0
+  %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x half> %y, <vscale x 4 x half> splat(half -0.000000e+00)
   %fadda = call half @llvm.vector.reduce.fadd.nxv4f16(half %x, <vscale x 4 x half> %sel)
   ret half %fadda
 }
@@ -80,9 +70,7 @@ define half @pred_fadda_nxv8f16(half %x, <vscale x 8 x half> %y, <vscale x 8 x i
 ; CHECK-NEXT:    fadda h0, p0, h0, z1.h
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
 ; CHECK-NEXT:    ret
-  %i = insertelement <vscale x 8 x half> poison, half -0.000000e+00, i32 0
-  %minus0 = shufflevector <vscale x 8 x half> %i, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
-  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x half> %y, <vscale x 8 x half> %minus0
+  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x half> %y, <vscale x 8 x half> splat(half -0.000000e+00)
   %fadda = call half @llvm.vector.reduce.fadd.nxv8f16(half %x, <vscale x 8 x half> %sel)
   ret half %fadda
 }

llvm/test/CodeGen/AArch64/sve-fold-loadext-and-splat-vector.ll

@@ -13,9 +13,7 @@ define <vscale x 2 x i64> @fold_loadext_and(ptr %ptr, i32 %needle, <vscale x 2 x
 ; CHECK-NEXT:    ret
   %load = load <vscale x 2 x i32>, ptr %ptr, align 4
   %ext = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
-  %splatinsert = insertelement <vscale x 2 x i64> poison, i64 4294967295, i64 0
-  %splat = shufflevector <vscale x 2 x i64> %splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
-  %and = and <vscale x 2 x i64> %ext, %splat
+  %and = and <vscale x 2 x i64> %ext, splat(i64 4294967295)
   ret <vscale x 2 x i64> %and
 }