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[AMDGPU] Add documentation files for GFX12. (llvm#157151)
This patch adds documentation files for GFX12.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX12.rst‎

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‎llvm/docs/AMDGPU/gfx12_addr.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx12_addr:
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addr
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====
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*Size:* 1 dword.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx12_attr.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx12_attr:
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attr
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====
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Interpolation attribute and channel:
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============== ===================================
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Syntax Description
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============== ===================================
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attr{0..32}.x Attribute 0..32 with *x* channel.
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attr{0..32}.y Attribute 0..32 with *y* channel.
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attr{0..32}.z Attribute 0..32 with *z* channel.
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attr{0..32}.w Attribute 0..32 with *w* channel.
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============== ===================================
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Examples:
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.. parsed-literal::
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ds_param_load v1, attr0.x

‎llvm/docs/AMDGPU/gfx12_clause.rst‎

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.. _amdgpu_synid_clause:
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clause
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======
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Description of a clause following this instruction.
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‎llvm/docs/AMDGPU/gfx12_data0_56f215.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx12_data0_56f215:
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data0
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=====
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Instruction input.
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*Size:* 3 dwords.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx12_data0_6802ce.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx12_data0_6802ce:
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data0
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=====
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Instruction input.
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*Size:* 1 dword.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx12_data0_e016a1.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx12_data0_e016a1:
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data0
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=====
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Instruction input.
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*Size:* 4 dwords.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx12_data0_fd235e.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx12_data0_fd235e:
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data0
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=====
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Instruction input.
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*Size:* 2 dwords.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx12_data1_6802ce.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx12_data1_6802ce:
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data1
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=====
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Instruction input.
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*Size:* 1 dword.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx12_data1_731030.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx12_data1_731030:
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data1
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=====
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Instruction input.
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*Size:* 8 dwords.
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*Operands:* :ref:`v<amdgpu_synid_v>`

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