diff --git a/README.md b/README.md
index d944c959..db1e71ef 100644
--- a/README.md
+++ b/README.md
@@ -1465,6 +1465,41 @@ init
 halt
 ```
 
+##### System Bus
+The EmbeddedRiscvJtag plugin can also be configured to support system bus accesses per the RISC-V Debug Specification v1.0. This allows memory access without impacting CPU execution and can be handy when a debug host is regularly polling (e.g. RTT logging).
+
+```scala
+new EmbeddedRiscvJtag(
+  p = DebugTransportModuleParameter(
+    addressWidth = 7,
+    version      = 1,
+    idle         = 7
+  ),
+  withTunneling = false,
+  withTap = true,
+  withSysBus = true
+)
+```
+
+Then connect `sysBus` to your logic just like a data bus (`sysBus` is a `DBusSimpleBus`).
+
+```scala
+var debugSysBus: Axi4Shared = null
+
+...
+
+for (plugin <- cpuConfig.plugins) plugin match {
+  case plugin: EmbeddedRiscvJtag => {
+    debugSysBus = plugin.sysBus.toAxi4Shared()
+  }
+  case _ =>
+}
+
+...
+
+// Connect debugSysBus to a crossbar, etc.
+```
+
 #### YamlPlugin
 
 This plugin offers a service to other plugins to generate a useful Yaml file describing the CPU configuration. It contains, for instance, the sequence of instructions required
diff --git a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
index 1e625b28..2b4051e8 100644
--- a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
+++ b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
@@ -16,7 +16,8 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
                         var debugCd : ClockDomain = null,
                         var jtagCd : ClockDomain = null,
                         var withTap : Boolean = true,
-                        var withTunneling : Boolean = false
+                        var withTunneling : Boolean = false,
+                        var withSysBus : Boolean = false
                         ) extends Plugin[VexRiscv] with VexRiscvRegressionArg{
 
 
@@ -25,6 +26,7 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
   var jtag : Jtag = null
   var jtagInstruction : JtagTapInstructionCtrl = null
   var ndmreset : Bool = null
+  var sysBus : DBusSimpleBus = null
 
 
   def setDebugCd(cd : ClockDomain) : this.type = {debugCd = cd; this}
@@ -48,9 +50,24 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
           xlen = XLEN,
           flen = pipeline.config.FLEN,
           withFpuRegAccess = pipeline.config.FLEN == 64
-        ))
-      )
+        )),
+        withSysBus = withSysBus
+      ),
     )
+    if (withSysBus) {
+      sysBus = master(DBusSimpleBus())
+
+      sysBus.cmd.valid := dm.io.sysBus.cmd.valid
+      dm.io.sysBus.cmd.ready := sysBus.cmd.ready
+      sysBus.cmd.payload.wr := dm.io.sysBus.cmd.wr
+      sysBus.cmd.payload.address := dm.io.sysBus.cmd.address
+      sysBus.cmd.payload.data := dm.io.sysBus.cmd.data
+      sysBus.cmd.payload.size := dm.io.sysBus.cmd.size
+
+      dm.io.sysBus.rsp.ready := sysBus.rsp.ready
+      dm.io.sysBus.rsp.error := sysBus.rsp.error
+      dm.io.sysBus.rsp.data := sysBus.rsp.data
+    }
 
     ndmreset := dm.io.ndmreset