Dealing with multi-instruction masks

[emesare]

Masking of instructions requires us to know that a constant is a pointer to a relocatable section. The issue is that in many RISCy architectures the pattern for loading a pointer will be split across multiple instructions. Identifying this pattern is very error prone if not done on an ISA level.

We should provide a way to register ISA specific handlers that can mask out instructions. This complicates the basic block GUID generation, however these functions wouldn't match regardless because the relocatable instructions weren't masked.

[emesare]

An example of the split pointer arithmetic from TriCore:

00000074  911000f8   movh.a  a15, 0x8001
00000078  d9ff6c38   lea     a15, a15, -0x7b14  {0x800084ec}

[emesare]

Another path forward is utilizing Binary Ninja's MLIL that would be able to identify these patterns and simplify them down to a constant pointer, the issue is that it is not portable. IDA and Ghidra would not be able to replicate that behavior.

[emesare]

Using MLIL here is extremely error prone, instead of that we should pattern match specific known multiple instruction variants.

These variants can be documented in the spec and adjusted as need be, they should be more strict however than the regular single instruction masking as its likely to accidentally mask of incidentals such as accesses into a structure or an array.

[emesare]

Closed with #30

See https://github.com/Vector35/warp?tab=readme-ov-file#what-is-considered-a-relocatable-instruction for more details.