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Description
I have created a project that will run on a ULX3S. This is intended as a test of the IDDR71B primitive to receive 7:1 geared LVDS data. And also as a independent test of errors I am seeing on a custom board. These errors are describe here #1511
When built using Lattice Diamond, it works as expected. However when build using Yosys and nextpnr, I am getting errors.
The project is based on the loopback test in 7:1 LVDS Video Interface for MachXO2/3 and ECP5. The file "ip_gddr71rx.v" has been replaced by logic produced by Clarity that comes with Diamond V3.13.
The original version of "ip_gddr71rx.v" used a PLL to recover the clock. This caused problems for 2 reasons. Firstly, nextpnr won't allow the D input of a IDDR71B and the CLKI input of a EHXPLLL to be connected to the same pin. Diamond does allow this. Secondly, I am running this with the LVDS clock at about 6MHz. This is below the minimum of 8MHz allowed for the CLKI input of a EHXPLLL. To get around this, "ip_gddr71rx.v" and "ip_gddr71tx.v" are using a common 21MHz edge clock. Sharing the same clock works for a loopback test.
I have left the Diamond version running for over an hour with no errors.
The Trellis version has errors in the received data.
With the transmitted value tx_a incrementing by 1 each cycle, errors are seen in the value of rx_a when the lower 4 bits are 0.
With the transmitted value tx_b decrementing by 1 each cycle, errors are seen in the value of rx_b when the lower 4 bits are ones.
Trellis project
ecp5_71lvds_loopback_demo_trellis.zip
Diamond project
ecp5_71lvds_loopback_demo_diamond.zip
bit file produced by Diamond
ecp5_71lvds_loopback_demo_diamond_bit.zip
Eight jumper wires are needed. Connect as follows (ordinary jumper wires appear to work ok due to the relatively low frequency used):
GP12 -> GP14
GN12 -> GN14
GP9 -> GP15
GN9 -> GN15
GP10 -> GP16
GN10 -> GN16
GP11 -> GP17
GN11 -> GN17
The F1 button is the reset.
The F2 button clears errors.
The dip switches change what is displayed on the LEDs.