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[GlobalISel] add KnownBits tracking for G_UMULH and G_SMULH (llvm#158445)
The code is taken from `SelectionDAG::computeKnownBits`. This ticks off `MULHU` and `MULHS` from llvm#150515
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-422
lines changed

8 files changed

+679
-422
lines changed

‎llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -344,6 +344,22 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
344344
Known = KnownBits::mul(Known, Known2);
345345
break;
346346
}
347+
case TargetOpcode::G_UMULH: {
348+
computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
349+
Depth + 1);
350+
computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
351+
Depth + 1);
352+
Known = KnownBits::mulhu(Known, Known2);
353+
break;
354+
}
355+
case TargetOpcode::G_SMULH: {
356+
computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
357+
Depth + 1);
358+
computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
359+
Depth + 1);
360+
Known = KnownBits::mulhs(Known, Known2);
361+
break;
362+
}
347363
case TargetOpcode::G_SELECT: {
348364
computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(),
349365
Known, DemandedElts, Depth + 1);

‎llvm/test/CodeGen/AArch64/GlobalISel/knownbits-smulh.mir‎

Lines changed: 137 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,137 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 6
2+
# RUN: llc -mtriple=aarch64 -passes='print<gisel-value-tracking>' -filetype=null %s 2>&1 | FileCheck %s
3+
4+
---
5+
name: Cst
6+
body: |
7+
bb.0:
8+
; CHECK-LABEL: name: @Cst
9+
; CHECK-NEXT: %0:_ KnownBits:00010011 SignBits:3
10+
; CHECK-NEXT: %1:_ KnownBits:11100000 SignBits:3
11+
; CHECK-NEXT: %2:_ KnownBits:11111101 SignBits:6
12+
%0:_(s8) = G_CONSTANT i8 19
13+
%1:_(s8) = G_CONSTANT i8 224
14+
%2:_(s8) = G_SMULH %0, %1
15+
...
16+
---
17+
name: CstZero
18+
body: |
19+
bb.0:
20+
; CHECK-LABEL: name: @CstZero
21+
; CHECK-NEXT: %0:_ KnownBits:11111111 SignBits:8
22+
; CHECK-NEXT: %1:_ KnownBits:00000000 SignBits:8
23+
; CHECK-NEXT: %2:_ KnownBits:00000000 SignBits:8
24+
%0:_(s8) = G_CONSTANT i8 255
25+
%1:_(s8) = G_CONSTANT i8 0
26+
%2:_(s8) = G_SMULH %0, %1
27+
...
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---
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name: ScalarVar
30+
body: |
31+
bb.0:
32+
; CHECK-LABEL: name: @ScalarVar
33+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
34+
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
35+
; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
36+
%0:_(s8) = COPY $b0
37+
%1:_(s8) = COPY $b1
38+
%2:_(s8) = G_SMULH %0, %1
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...
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---
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name: ScalarZero
42+
body: |
43+
bb.0:
44+
; CHECK-LABEL: name: @ScalarZero
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; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
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; CHECK-NEXT: %1:_ KnownBits:00000000 SignBits:8
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; CHECK-NEXT: %2:_ KnownBits:00000000 SignBits:8
48+
%0:_(s8) = COPY $b0
49+
%1:_(s8) = G_CONSTANT i8 0
50+
%2:_(s8) = G_SMULH %0, %1
51+
...
52+
---
53+
name: ScalarVarAbs
54+
body: |
55+
bb.0:
56+
; CHECK-LABEL: name: @ScalarVarAbs
57+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
58+
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
59+
; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:9
60+
; CHECK-NEXT: %3:_ KnownBits:0000000000000001 SignBits:15
61+
; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
62+
%0:_(s8) = COPY $b0
63+
%1:_(s8) = G_ABS %0
64+
%2:_(s16) = G_SEXT %1
65+
%3:_(s16) = G_CONSTANT i16 1
66+
%4:_(s16) = G_SMULH %2, %3
67+
...
68+
---
69+
name: SplatVecCst
70+
body: |
71+
bb.0:
72+
; CHECK-LABEL: name: @SplatVecCst
73+
; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5
74+
; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5
75+
; CHECK-NEXT: %2:_ KnownBits:11111010 SignBits:5
76+
; CHECK-NEXT: %3:_ KnownBits:00000000 SignBits:8
77+
%0:_(s8) = G_CONSTANT i8 250
78+
%1:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %0(s8)
79+
%2:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %0(s8)
80+
%3:_(<vscale x 16 x s8>) = G_SMULH %1, %2
81+
...
82+
---
83+
name: SplatVecPartScalar
84+
body: |
85+
bb.0:
86+
; CHECK-LABEL: name: @SplatVecPartScalar
87+
; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5
88+
; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5
89+
; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
90+
; CHECK-NEXT: %3:_ KnownBits:00001111 SignBits:4
91+
; CHECK-NEXT: %4:_ KnownBits:0000???? SignBits:4
92+
; CHECK-NEXT: %5:_ KnownBits:0000???? SignBits:4
93+
; CHECK-NEXT: %6:_ KnownBits:???????? SignBits:1
94+
%0:_(s8) = G_CONSTANT i8 250
95+
%1:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %0(s8)
96+
%2:_(s8) = G_IMPLICIT_DEF
97+
%3:_(s8) = G_CONSTANT i8 15
98+
%4:_(s8) = G_AND %2, %3
99+
%5:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %4(s8)
100+
%6:_(<vscale x 16 x s8>) = G_SMULH %1, %5
101+
...
102+
---
103+
name: VecCst
104+
body: |
105+
bb.0:
106+
; CHECK-LABEL: name: @VecCst
107+
; CHECK-NEXT: %0:_ KnownBits:00011001 SignBits:3
108+
; CHECK-NEXT: %1:_ KnownBits:11100001 SignBits:3
109+
; CHECK-NEXT: %2:_ KnownBits:?????001 SignBits:3
110+
; CHECK-NEXT: %3:_ KnownBits:?????001 SignBits:3
111+
; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:1
112+
%0:_(s8) = G_CONSTANT i8 25
113+
%1:_(s8) = G_CONSTANT i8 225
114+
%2:_(<2 x s8>) = G_BUILD_VECTOR %0:_(s8), %1:_(s8)
115+
%3:_(<2 x s8>) = G_BUILD_VECTOR %0:_(s8), %1:_(s8)
116+
%4:_(<2 x s8>) = G_SMULH %2, %3
117+
...
118+
---
119+
name: VecPartScalar
120+
body: |
121+
bb.0:
122+
; CHECK-LABEL: name: @VecPartScalar
123+
; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5
124+
; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5
125+
; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
126+
; CHECK-NEXT: %3:_ KnownBits:00001111 SignBits:4
127+
; CHECK-NEXT: %4:_ KnownBits:0000???? SignBits:4
128+
; CHECK-NEXT: %5:_ KnownBits:0000???? SignBits:4
129+
; CHECK-NEXT: %6:_ KnownBits:???????? SignBits:1
130+
%0:_(s8) = G_CONSTANT i8 250
131+
%1:_(<2 x s8>) = G_BUILD_VECTOR %0:_(s8), %0:_(s8)
132+
%2:_(s8) = G_IMPLICIT_DEF
133+
%3:_(s8) = G_CONSTANT i8 15
134+
%4:_(s8) = G_AND %2, %3
135+
%5:_(<2 x s8>) = G_BUILD_VECTOR %4:_(s8), %4:_(s8)
136+
%6:_(<2 x s8>) = G_SMULH %1, %5
137+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/knownbits-umulh.mir‎

Lines changed: 137 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,137 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 6
2+
# RUN: llc -mtriple=aarch64 -passes='print<gisel-value-tracking>' -filetype=null %s 2>&1 | FileCheck %s
3+
4+
---
5+
name: Cst
6+
body: |
7+
bb.0:
8+
; CHECK-LABEL: name: @Cst
9+
; CHECK-NEXT: %0:_ KnownBits:00010011 SignBits:3
10+
; CHECK-NEXT: %1:_ KnownBits:11100000 SignBits:3
11+
; CHECK-NEXT: %2:_ KnownBits:00010000 SignBits:3
12+
%0:_(s8) = G_CONSTANT i8 19
13+
%1:_(s8) = G_CONSTANT i8 224
14+
%2:_(s8) = G_UMULH %0, %1
15+
...
16+
---
17+
name: CstZero
18+
body: |
19+
bb.0:
20+
; CHECK-LABEL: name: @CstZero
21+
; CHECK-NEXT: %0:_ KnownBits:11111111 SignBits:8
22+
; CHECK-NEXT: %1:_ KnownBits:00000000 SignBits:8
23+
; CHECK-NEXT: %2:_ KnownBits:00000000 SignBits:8
24+
%0:_(s8) = G_CONSTANT i8 255
25+
%1:_(s8) = G_CONSTANT i8 0
26+
%2:_(s8) = G_UMULH %0, %1
27+
...
28+
---
29+
name: ScalarVar
30+
body: |
31+
bb.0:
32+
; CHECK-LABEL: name: @ScalarVar
33+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
34+
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
35+
; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
36+
%0:_(s8) = COPY $b0
37+
%1:_(s8) = COPY $b1
38+
%2:_(s8) = G_UMULH %0, %1
39+
...
40+
---
41+
name: ScalarZero
42+
body: |
43+
bb.0:
44+
; CHECK-LABEL: name: @ScalarZero
45+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
46+
; CHECK-NEXT: %1:_ KnownBits:00000000 SignBits:8
47+
; CHECK-NEXT: %2:_ KnownBits:00000000 SignBits:8
48+
%0:_(s8) = COPY $b0
49+
%1:_(s8) = G_CONSTANT i8 0
50+
%2:_(s8) = G_UMULH %0, %1
51+
...
52+
---
53+
name: ScalarVarAbs
54+
body: |
55+
bb.0:
56+
; CHECK-LABEL: name: @ScalarVarAbs
57+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
58+
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
59+
; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:9
60+
; CHECK-NEXT: %3:_ KnownBits:0000000000000001 SignBits:15
61+
; CHECK-NEXT: %4:_ KnownBits:0000000000000000 SignBits:16
62+
%0:_(s8) = COPY $b0
63+
%1:_(s8) = G_ABS %0
64+
%2:_(s16) = G_SEXT %1
65+
%3:_(s16) = G_CONSTANT i16 1
66+
%4:_(s16) = G_UMULH %2, %3
67+
...
68+
---
69+
name: SplatVecCst
70+
body: |
71+
bb.0:
72+
; CHECK-LABEL: name: @SplatVecCst
73+
; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5
74+
; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5
75+
; CHECK-NEXT: %2:_ KnownBits:11111010 SignBits:5
76+
; CHECK-NEXT: %3:_ KnownBits:11110100 SignBits:4
77+
%0:_(s8) = G_CONSTANT i8 250
78+
%1:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %0(s8)
79+
%2:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %0(s8)
80+
%3:_(<vscale x 16 x s8>) = G_UMULH %1, %2
81+
...
82+
---
83+
name: SplatVecPartScalar
84+
body: |
85+
bb.0:
86+
; CHECK-LABEL: name: @SplatVecPartScalar
87+
; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5
88+
; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5
89+
; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
90+
; CHECK-NEXT: %3:_ KnownBits:00001111 SignBits:4
91+
; CHECK-NEXT: %4:_ KnownBits:0000???? SignBits:4
92+
; CHECK-NEXT: %5:_ KnownBits:0000???? SignBits:4
93+
; CHECK-NEXT: %6:_ KnownBits:0000???? SignBits:4
94+
%0:_(s8) = G_CONSTANT i8 250
95+
%1:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %0(s8)
96+
%2:_(s8) = G_IMPLICIT_DEF
97+
%3:_(s8) = G_CONSTANT i8 15
98+
%4:_(s8) = G_AND %2, %3
99+
%5:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %4(s8)
100+
%6:_(<vscale x 16 x s8>) = G_UMULH %1, %5
101+
...
102+
---
103+
name: VecCst
104+
body: |
105+
bb.0:
106+
; CHECK-LABEL: name: @VecCst
107+
; CHECK-NEXT: %0:_ KnownBits:00011001 SignBits:3
108+
; CHECK-NEXT: %1:_ KnownBits:11100001 SignBits:3
109+
; CHECK-NEXT: %2:_ KnownBits:?????001 SignBits:3
110+
; CHECK-NEXT: %3:_ KnownBits:?????001 SignBits:3
111+
; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:1
112+
%0:_(s8) = G_CONSTANT i8 25
113+
%1:_(s8) = G_CONSTANT i8 225
114+
%2:_(<2 x s8>) = G_BUILD_VECTOR %0:_(s8), %1:_(s8)
115+
%3:_(<2 x s8>) = G_BUILD_VECTOR %0:_(s8), %1:_(s8)
116+
%4:_(<2 x s8>) = G_UMULH %2, %3
117+
...
118+
---
119+
name: VecPartScalar
120+
body: |
121+
bb.0:
122+
; CHECK-LABEL: name: @VecPartScalar
123+
; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5
124+
; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5
125+
; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
126+
; CHECK-NEXT: %3:_ KnownBits:00001111 SignBits:4
127+
; CHECK-NEXT: %4:_ KnownBits:0000???? SignBits:4
128+
; CHECK-NEXT: %5:_ KnownBits:0000???? SignBits:4
129+
; CHECK-NEXT: %6:_ KnownBits:0000???? SignBits:4
130+
%0:_(s8) = G_CONSTANT i8 250
131+
%1:_(<2 x s8>) = G_BUILD_VECTOR %0:_(s8), %0:_(s8)
132+
%2:_(s8) = G_IMPLICIT_DEF
133+
%3:_(s8) = G_CONSTANT i8 15
134+
%4:_(s8) = G_AND %2, %3
135+
%5:_(<2 x s8>) = G_BUILD_VECTOR %4:_(s8), %4:_(s8)
136+
%6:_(<2 x s8>) = G_UMULH %1, %5
137+
...

‎llvm/test/CodeGen/AArch64/pr58431.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ define i32 @f(i64 %0) {
99
; CHECK-NEXT: mov w10, #10 // =0xa
1010
; CHECK-NEXT: eor x8, x8, #0x8000000000000003
1111
; CHECK-NEXT: umulh x8, x9, x8
12-
; CHECK-NEXT: msub x0, x8, x10, x9
12+
; CHECK-NEXT: umsubl x0, w8, w10, x9
1313
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
1414
; CHECK-NEXT: ret
1515
%2 = trunc i64 %0 to i32

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