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caosjrcaosjr
committed
update: review fixes
Signed-off-by: Carlos Souza <[email protected]>
1 parent 7641442 commit 1b35e5b

13 files changed

+108
-107
lines changed

‎projects/ad4630_fmc/common/ad463x_bd.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ set DDR_EN $ad_project_params(DDR_EN)
1313
set INTERLEAVE_MODE $ad_project_params(INTERLEAVE_MODE)
1414

1515
if {$INTERLEAVE_MODE == 1} {
16-
if {$LANES_PER_CHANNEL > 1 || $NUM_OF_CHANNEL != 2} {
16+
if {$LANES_PER_CHANNEL != 1 || $NUM_OF_CHANNEL != 2} {
1717
puts "ERROR: Interleave mode is only supported with 2 channels (NUM_OF_CHANNEL == 2) and 1 lane per channel (LANES_PER_CHANNEL == 1)."
1818
exit 2
1919
}

‎projects/ad4630_fmc/zed/Makefile‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,19 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
66

77
PROJECT_NAME := ad4630_fmc_zed
88

9-
M_DEPS += system_constr_4sdi_2ch.xdc
10-
M_DEPS += system_constr_4sdi_1ch.xdc
11-
M_DEPS += system_constr_2sdi_2ch.xdc
12-
M_DEPS += system_constr_2sdi_1ch.xdc
13-
M_DEPS += system_constr_1sdi_2ch_interleave.xdc
14-
M_DEPS += system_constr_1sdi_2ch.xdc
159
M_DEPS += system_constr_1sdi_1ch.xdc
10+
M_DEPS += system_constr_1sdi_2ch_interleave.xdc
11+
M_DEPS += system_constr_2sdi_1ch.xdc
12+
M_DEPS += system_constr_2sdi_2ch.xdc
13+
M_DEPS += system_constr_4sdi_1ch.xdc
14+
M_DEPS += system_constr_4sdi_2ch.xdc
15+
M_DEPS += system_constr_8sdi_2ch.xdc
16+
1617
M_DEPS += ../common/ad463x_bd.tcl
1718
M_DEPS += ../../scripts/adi_pd.tcl
1819
M_DEPS += ../../common/zed/zed_system_constr.xdc

‎projects/ad4630_fmc/zed/system_constr.xdc‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,25 @@
11
###############################################################################
2-
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

66
# ad463x_fmc SPI interface
7-
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] ; ## C11 FMC_LA06_N
8-
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk] ; ## G6 FMC_LA00_CC_P
9-
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs] ; ## G7 FMC_LA00_CC_N
10-
11-
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_echo_sclk] ; ## D20 FMC_LA17_CC_P
12-
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_resetn] ; ## D9 FMC_LA01_CC_N
13-
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy] ; ## C22 FMC_LA18_CC_P
14-
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LA01_CC_P
15-
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_CLK0_P
16-
17-
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC-LA08_P
18-
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC-LA08_N
19-
20-
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC-LA07_P
21-
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC-LA07_N
22-
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC-LA17_N_CC
7+
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] ; ## C11 FMC_LPC_LA06_N
8+
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk] ; ## G6 FMC_LPC_LA00_CC_P
9+
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs] ; ## G7 FMC_LPC_LA00_CC_N
10+
11+
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_echo_sclk] ; ## D20 FMC_LPC_LA17_CC_P
12+
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_resetn] ; ## D9 FMC_LPC_LA01_CC_N
13+
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy] ; ## C22 FMC_LPC_LA18_CC_P
14+
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LPC_LA01_CC_P
15+
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_LPC_CLK0_P
16+
17+
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC_LPC_LA08_P
18+
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC_LPC_LA08_N
19+
20+
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC_LPC_LA07_P
21+
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC_LPC_LA07_N
22+
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC_LPC_LA17_N_CC
2323

2424
# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency
2525
create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_ext_clk]

‎projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -10,7 +10,7 @@
1010
set tsetup 5.6
1111
set thold 1.4
1212

13-
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi}] ; ## H07 FMC_LA02_P
13+
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi}] ; ## H07 FMC_LPC_LA02_P
1414

1515
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi]
16-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi]
16+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi]

‎projects/ad4630_fmc/zed/system_constr_1sdi_2ch.xdc‎

Lines changed: 0 additions & 20 deletions
This file was deleted.

‎projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -11,7 +11,7 @@
1111
set tsetup 5.6
1212
set thold 1.4
1313

14-
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P
14+
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P
1515

1616
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}]
17-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}]
17+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}]

‎projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -10,10 +10,10 @@
1010
set tsetup 5.6
1111
set thold 1.4
1212

13-
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P
14-
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LA02_N
13+
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P
14+
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LPC_LA02_N
1515

1616
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]]
1717
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]]
1818
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]]
19-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]]
19+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]]

‎projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,20 @@
11
###############################################################################
2-
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
# Constraints for 2 SDI per channel, 2 Channels configuration (4 SDI lines total)
6+
# Constraints for 1 SDI per channel, 2 Channels configuration with reorder (NO_REORDER=0)
7+
# This results in 2 SDI lines total
78
# input delays for MISO lines (SDO for the device)
89
# data is latched on negative edge
910

1011
set tsetup 5.6
1112
set thold 1.4
1213

13-
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P
14-
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LA02_N
15-
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] ; ## H10 FMC_LA04_P
16-
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] ; ## H11 FMC_LA04_N
14+
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P
15+
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H10 FMC_LPC_LA04_P
1716

1817
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}]
1918
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}]
2019
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}]
2120
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}]
22-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[2]}]
23-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}]
24-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}]
25-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}]

‎projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -22,4 +22,4 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_p
2222
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[2]]
2323
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[2]]
2424
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[3]]
25-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]]
25+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]]

‎projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc‎

Lines changed: 15 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,25 @@
11
###############################################################################
2-
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
# Constraints for 4 SDI per channel, 2 Channels configuration (8 SDI lines total)
6+
# Constraints for 2 SDI per channel, 2 Channels configuration (4 SDI lines total)
77
# input delays for MISO lines (SDO for the device)
88
# data is latched on negative edge
99

1010
set tsetup 5.6
11-
set thold 1.6
11+
set thold 1.4
1212

13-
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
14-
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N
15-
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P
16-
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[3]] ; ## G10 FMC_LPC_LA03_N
17-
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[4]] ; ## H10 FMC_LPC_LA04_P
18-
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[5]] ; ## H11 FMC_LPC_LA04_N
19-
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[6]] ; ## D11 FMC_LPC_LA05_P
20-
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[7]] ; ## D12 FMC_LPC_LA05_N
13+
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P
14+
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LPC_LA02_N
15+
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] ; ## H10 FMC_LPC_LA04_P
16+
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] ; ## H11 FMC_LPC_LA04_N
2117

22-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]]
23-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]]
24-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]]
25-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]]
26-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[2]]
27-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[2]]
28-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[3]]
29-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]]
30-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[4]]
31-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[4]]
32-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[5]]
33-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[5]]
34-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[6]]
35-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[6]]
36-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[7]]
37-
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]]
18+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}]
19+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}]
20+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}]
21+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}]
22+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[2]}]
23+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}]
24+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}]
25+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}]

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