Skip to content

Commit cd6b380

Browse files
committed
projects/xcvr_wizard: Add xcvr_wizard READMEs
Signed-off-by: Elena-Hadarau_adi <[email protected]>
1 parent 7c58302 commit cd6b380

File tree

6 files changed

+142
-0
lines changed

6 files changed

+142
-0
lines changed

projects/xcvr_wizard/README.md

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
# XCVR-WIZARD HDL Project
2+
3+
- HDL project documentation: https://analogdevicesinc.github.io/hdl/library/jesd204/xgt_wizard/index.html
4+
5+
## Building the project
6+
7+
This project is used internally to generate transceiver configuration files for
8+
Xilinx carriers. The generated configuration files are later parsed and used by
9+
other HDL projects (e.g., ADRV9009, DAQ2, DAQ3).
10+
Please enter the folder for the FPGA carrier you want to use
11+
and read the README.md.
Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
<!-- no_build_example, no_dts, no_no_os -->
2+
3+
# XCVR-WIZARD/KC705 HDL Project
4+
5+
- Transceiver type: GTXE2
6+
7+
## Building the project
8+
9+
```
10+
cd projects/xcvr_wizard/kc705
11+
make
12+
```
13+
14+
If other configurations are desired, then the parameters from the HDL project
15+
(see below) need to be changed.
16+
17+
The overwritable parameters from the environment:
18+
19+
- LANE_RATE: Value of lane rate [gbps]
20+
- REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40)
21+
- PLL_TYPE: The PLL used for driving the link [CPLL/QPLL]
22+
23+
Note: When running make with parameters, a new folder specific to the chosen
24+
configuration is created under the project directory. The generated IPs and
25+
the corresponding configuration files (e.g. *_cfng.txt) will be placed there.
26+
27+
- Generated files: `<config_folder>/<project_name>.gen/sources_1/ip/*_cfng.txt`
Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
<!-- no_build_example, no_dts, no_no_os -->
2+
3+
# XCVR-WIZARD/KCU105 HDL Project
4+
5+
- Transceiver type: GTHE3
6+
7+
## Building the project
8+
9+
```
10+
cd projects/xcvr_wizard/kcu105
11+
make
12+
```
13+
14+
If other configurations are desired, then the parameters from the HDL project (see below) need to be changed.
15+
16+
The overwritable parameters from the environment:
17+
18+
- LANE_RATE: Value of lane rate [gbps]
19+
- REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40)
20+
- PLL_TYPE: The PLL used for driving the link [CPLL/QPLL]
21+
22+
Note: When running make with parameters, a new folder specific to the chosen
23+
configuration is created under the project directory. The generated IPs and
24+
the corresponding configuration files (e.g. *_cfng.txt) will be placed there.
25+
26+
- Generated files: `<config_folder>/<project_name>.gen/sources_1/ip/*_cfng.txt`
Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
<!-- no_build_example, no_dts, no_no_os -->
2+
3+
# XCVR-WIZARD/VCU118 HDL Project
4+
5+
- Transceiver type: GTYE4
6+
7+
## Building the project
8+
9+
```
10+
cd projects/xcvr_wizard/vcu118
11+
make
12+
```
13+
14+
If other configurations are desired, then the parameters from the HDL project (see below) need to be changed.
15+
16+
The overwritable parameters from the environment:
17+
18+
- LANE_RATE: Value of lane rate [gbps]
19+
- REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40)
20+
- PLL_TYPE: The PLL used for driving the link [CPLL/QPLL]
21+
22+
Note: When running make with parameters, a new folder specific to the chosen
23+
configuration is created under the project directory. The generated IPs and
24+
the corresponding configuration files (e.g. *_cfng.txt) will be placed there.
25+
26+
- Generated files: `<config_folder>/<project_name>.gen/sources_1/ip/*_cfng.txt`
Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
<!-- no_build_example, no_dts, no_no_os -->
2+
3+
# XCVR-WIZARD/ZC706 HDL Project
4+
5+
- Transceiver type: GTXE2
6+
7+
## Building the project
8+
9+
```
10+
cd projects/xcvr_wizard/zc706
11+
make
12+
```
13+
14+
If other configurations are desired, then the parameters from the HDL project (see below) need to be changed.
15+
16+
The overwritable parameters from the environment:
17+
18+
- LANE_RATE: Value of lane rate [gbps]
19+
- REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40)
20+
- PLL_TYPE: The PLL used for driving the link [CPLL/QPLL]
21+
22+
Note: When running make with parameters, a new folder specific to the chosen
23+
configuration is created under the project directory. The generated IPs and
24+
the corresponding configuration files (e.g. *_cfng.txt) will be placed there.
25+
26+
- Generated files: `<config_folder>/<project_name>.gen/sources_1/ip/*_cfng.txt`
Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
<!-- no_build_example, no_dts, no_no_os -->
2+
3+
# XCVR-WIZARD/ZCU102 HDL Project
4+
5+
- Transceiver type: GTHE4
6+
7+
## Building the project
8+
9+
```
10+
cd projects/xcvr_wizard/zcu102
11+
make
12+
```
13+
14+
If other configurations are desired, then the parameters from the HDL project (see below) need to be changed.
15+
16+
The overwritable parameters from the environment:
17+
18+
- LANE_RATE: Value of lane rate [gbps]
19+
- REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40)
20+
- PLL_TYPE: The PLL used for driving the link [CPLL/QPLL]
21+
22+
Note: When running make with parameters, a new folder specific to the chosen
23+
configuration is created under the project directory. The generated IPs and
24+
the corresponding configuration files (e.g. *_cfng.txt) will be placed there.
25+
26+
- Generated files: `<config_folder>/<project_name>.gen/sources_1/ip/*_cfng.txt`

0 commit comments

Comments
 (0)