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axi_tdd: Add testbench for the Generic TDD engine
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‎axi_tdd/Makefile‎

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####################################################################################
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####################################################################################
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## Copyright 2022(c) Analog Devices, Inc.
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####################################################################################
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####################################################################################
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# All test-bench dependencies except test programs
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SV_DEPS += ../common/sv/utils.svh
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SV_DEPS += ../common/sv/logger_pkg.sv
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SV_DEPS += ../common/sv/reg_accessor.sv
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SV_DEPS += ../common/sv/m_axis_sequencer.sv
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SV_DEPS += ../common/sv/s_axis_sequencer.sv
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SV_DEPS += ../common/sv/m_axi_sequencer.sv
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SV_DEPS += ../common/sv/s_axi_sequencer.sv
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SV_DEPS += ../common/sv/adi_regmap_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_tdd_gen_pkg.sv
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SV_DEPS += ../common/sv/test_harness_env.sv
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SV_DEPS += system_tb.sv
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ENV_DEPS += system_project.tcl
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ENV_DEPS += system_bd.tcl
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ENV_DEPS +=../scripts/adi_sim.tcl
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ENV_DEPS +=../scripts/run_sim.tcl
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LIB_DEPS += axi_tdd
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# default test program
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TP := test_program
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# config files should have the following format
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# cfg_<param1>_<param2>.tcl
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CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
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#$(warning $(CFG_FILES))
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# List of tests and configuration combinations that has to be run
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# Format is: <configuration>:<test name>
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TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
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#TESTS += cfg1_mm2mm_default:directed_test
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#TESTS += cfg1:test_program
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#TESTS += cfg2_fsync:test_program
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#TESTS += cfg2_fsync:test_frame_delay
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include ../scripts/project-sim.mk
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# usage :
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#
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# run specific test on a specific configuration in gui mode
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# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui
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#
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# run all test from a configuration
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# make cfg1_mm2mm_default
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####################################################################################
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####################################################################################

‎axi_tdd/README.md‎

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Usage :
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Run all tests in batch mode:
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make
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Run all tests in GUI mode:
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make MODE=gui
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Run specific test on a specific configuration in gui mode:
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make CFG=<name of cfg> TST=<name of test> MODE=gui
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Run all test from a configuration:
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make <name of cfg>
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Where:
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* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
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* <name of test> is a file from the tests directory without the tcl extension
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‎axi_tdd/cfgs/cfg1.tcl‎

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global ad_project_params
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set tdd_cfg [list \
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ID 0 \
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CHANNEL_COUNT 8 \
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REGISTER_WIDTH 32 \
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BURST_COUNT_WIDTH 32 \
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SYNC_EXTERNAL 1 \
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SYNC_INTERNAL 1 \
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SYNC_EXTERNAL_CDC 1 \
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SYNC_COUNT_WIDTH 64 \
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]
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‎axi_tdd/system_bd.tcl‎

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# ***************************************************************************
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# ***************************************************************************
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# Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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source ../../scripts/adi_env.tcl
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# Device clk
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ad_ip_instance clk_vip device_clk_vip [ list \
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INTERFACE_MODE {MASTER} \
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FREQ_HZ 250000000 \
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]
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adi_sim_add_define "DEVICE_CLK=device_clk_vip"
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set device_clk device_clk_vip/clk_out
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# ------------------
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#
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# Blocks under test
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#
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# ------------------
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global tdd_cfg
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ad_ip_instance axi_tdd dut_tdd $tdd_cfg
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ad_connect $device_clk dut_tdd/clk
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ad_connect $sys_cpu_resetn dut_tdd/resetn
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create_bd_port -dir I sync_in
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create_bd_port -dir O sync_out
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ad_connect sync_in dut_tdd/sync_in
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ad_connect sync_out dut_tdd/sync_out
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set num_ch [lindex $tdd_cfg 3]
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create_bd_port -from 0 -to [expr $num_ch-1] -dir O tdd_channel
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ad_connect tdd_channel dut_tdd/tdd_channel
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ad_cpu_interconnect 0x7c420000 dut_tdd
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‎axi_tdd/system_project.tcl‎

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source ../scripts/adi_sim.tcl
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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if {$argc < 1} {
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puts "Expecting at least one argument that specifies the test configuration"
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exit 1
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} else {
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set cfg_file [lindex $argv 0]
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}
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# Read config file
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source "cfgs/${cfg_file}"
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# Set the project name
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set project_name [file rootname $cfg_file]
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# Create the project
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adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e"
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# Add test files to the project
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adi_sim_project_files [list \
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"../common/sv/utils.svh" \
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"../common/sv/logger_pkg.sv" \
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"../common/sv/reg_accessor.sv" \
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"../common/sv/m_axis_sequencer.sv" \
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"../common/sv/s_axis_sequencer.sv" \
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"../common/sv/m_axi_sequencer.sv" \
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"../common/sv/s_axi_sequencer.sv" \
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"../common/sv/adi_regmap_pkg.sv" \
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"../common/sv/adi_regmap_tdd_gen_pkg.sv" \
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"../common/sv/test_harness_env.sv" \
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"tests/test_program.sv" \
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"system_tb.sv" \
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]
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#set a default test program
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adi_sim_add_define "TEST_PROGRAM=test_program"
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adi_sim_generate $project_name

‎axi_tdd/system_tb.sv‎

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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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`include "utils.svh"
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module system_tb();
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logic sync_in = 1'b0;
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logic [31:0] tdd_channel;
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`TEST_PROGRAM test();
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test_harness `TH (
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.sync_in (sync_in), //-dir I
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.sync_out (sync_out), //-dir O
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.tdd_channel (tdd_channel)
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);
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endmodule

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