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mimxrt/eth: Add DP83867 PHY driver support.
Adds new PHY driver for TI DP83867 Gigabit Ethernet PHY. Signed-off-by: Andrew Leech <[email protected]>
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‎ports/mimxrt/Makefile‎

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@@ -113,6 +113,7 @@ SRC_ETH_C += \
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$(MCUX_SDK_DIR)/drivers/enet/fsl_enet.c \
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hal/phy/device/phydp83825/fsl_phydp83825.c \
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hal/phy/device/phydp83848/fsl_phydp83848.c \
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hal/phy/device/phydp83867/fsl_phydp83867.c \
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hal/phy/device/phyksz8081/fsl_phyksz8081.c \
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hal/phy/device/phylan8720/fsl_phylan8720.c \
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hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.c \

‎ports/mimxrt/eth.c‎

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@@ -44,6 +44,7 @@
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#include "hal/phy/device/phyksz8081/fsl_phyksz8081.h"
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#include "hal/phy/device/phydp83825/fsl_phydp83825.h"
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#include "hal/phy/device/phydp83848/fsl_phydp83848.h"
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#include "hal/phy/device/phydp83867/fsl_phydp83867.h"
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#include "hal/phy/device/phylan8720/fsl_phylan8720.h"
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#include "hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.h"
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@@ -422,7 +423,7 @@ void eth_init_1(eth_t *self, int eth_id, const phy_operations_t *phy_ops, int ph
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uint32_t source_clock = eth_clock_init(eth_id, phy_clock);
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const machine_pin_obj_t *reset_pin = NULL;
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#if defined(pin_ENET_1_INT)
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#if defined(pin_ENET_1_RESET)
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reset_pin = pin_ENET_1_RESET;
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#endif
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const machine_pin_obj_t *int_pin = NULL;

‎ports/mimxrt/hal/phy/device/phydp83867/fsl_phydp83867.c‎

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/*
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* Copyright 2025 Planet Innovation
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* All rights reserved.
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*
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* Based on NXP RTL8211F driver structure and TI DP83867 specifications.
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_phydp83867.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Defines the PHY DP83867 vendor defined registers. */
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#define PHY_PHYSTS_REG 0x11U /*!< The PHY Status register. */
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/*! @brief Defines the PHY DP83867 ID number. */
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#define PHY_CONTROL_ID1 0x2000U /*!< The PHY ID1 (upper 16 bits). */
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#define PHY_CONTROL_ID2 0xA231U /*!< The PHY ID2 (lower 16 bits). */
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#define PHY_FULL_ID 0x2000A231U /*!< Full PHY ID. */
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/*! @brief Defines the mask flag in PHYSTS register. */
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#define PHY_PHYSTS_LINKSTATUS_MASK 0x0400U /*!< The PHY link status mask. */
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#define PHY_PHYSTS_LINKSPEED_MASK 0xC000U /*!< The PHY link speed mask. */
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#define PHY_PHYSTS_LINKDUPLEX_MASK 0x2000U /*!< The PHY link duplex mask. */
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#define PHY_PHYSTS_LINKSPEED_SHIFT 14U /*!< The link speed shift */
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/*! @brief Link speed values from PHYSTS register. */
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#define PHY_PHYSTS_LINKSPEED_10M 0U /*!< 10M link speed. */
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#define PHY_PHYSTS_LINKSPEED_100M 1U /*!< 100M link speed. */
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#define PHY_PHYSTS_LINKSPEED_1000M 2U /*!< 1000M link speed. */
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/*! @brief Defines the timeout macro. */
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#define PHY_READID_TIMEOUT_COUNT 1000U
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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const phy_operations_t phydp83867_ops = {.phyInit = PHY_DP83867_Init,
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.phyWrite = PHY_DP83867_Write,
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.phyRead = PHY_DP83867_Read,
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.getAutoNegoStatus = PHY_DP83867_GetAutoNegotiationStatus,
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.getLinkStatus = PHY_DP83867_GetLinkStatus,
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.getLinkSpeedDuplex = PHY_DP83867_GetLinkSpeedDuplex,
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.setLinkSpeedDuplex = PHY_DP83867_SetLinkSpeedDuplex,
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.enableLoopback = PHY_DP83867_EnableLoopback};
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/*******************************************************************************
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* Code
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******************************************************************************/
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status_t PHY_DP83867_Init(phy_handle_t *handle, const phy_config_t *config) {
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uint32_t counter = PHY_READID_TIMEOUT_COUNT;
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status_t result;
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uint32_t regValue = 0U;
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/* Init MDIO interface. */
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MDIO_Init(handle->mdioHandle);
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/* Assign phy address. */
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handle->phyAddr = config->phyAddr;
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/* Check PHY ID. */
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do
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{
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_ID1_REG, &regValue);
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if (result != kStatus_Success) {
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return result;
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}
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counter--;
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} while ((regValue != PHY_CONTROL_ID1) && (counter != 0U));
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if (counter == 0U) {
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return kStatus_Fail;
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}
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/* Reset PHY. */
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
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if (result != kStatus_Success) {
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return result;
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}
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/* Wait for reset to complete */
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counter = PHY_READID_TIMEOUT_COUNT;
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do {
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
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if (result != kStatus_Success) {
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return result;
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}
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counter--;
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} while ((regValue & PHY_BCTL_RESET_MASK) && (counter != 0U));
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if (counter == 0U) {
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return kStatus_Fail;
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}
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if (config->autoNeg) {
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/* Set the auto-negotiation. */
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result =
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MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_AUTONEG_ADVERTISE_REG,
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PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK |
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PHY_10BASETX_HALFDUPLEX_MASK | PHY_IEEE802_3_SELECTOR_MASK);
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if (result == kStatus_Success) {
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_1000BASET_CONTROL_REG,
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PHY_1000BASET_FULLDUPLEX_MASK);
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if (result == kStatus_Success) {
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
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if (result == kStatus_Success) {
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
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(regValue | PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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}
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} else {
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/* Disable isolate mode */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
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if (result != kStatus_Success) {
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return result;
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}
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regValue &= ~PHY_BCTL_ISOLATE_MASK;
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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if (result != kStatus_Success) {
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return result;
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}
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/* Disable the auto-negotiation and set user-defined speed/duplex configuration. */
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result = PHY_DP83867_SetLinkSpeedDuplex(handle, config->speed, config->duplex);
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}
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return result;
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}
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status_t PHY_DP83867_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data) {
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return MDIO_Write(handle->mdioHandle, handle->phyAddr, phyReg, data);
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}
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status_t PHY_DP83867_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr) {
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return MDIO_Read(handle->mdioHandle, handle->phyAddr, phyReg, dataPtr);
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}
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status_t PHY_DP83867_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status) {
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assert(status);
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status_t result;
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uint32_t regValue;
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*status = false;
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/* Check auto negotiation complete. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, &regValue);
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if (result == kStatus_Success) {
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if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U) {
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*status = true;
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}
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}
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return result;
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}
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status_t PHY_DP83867_GetLinkStatus(phy_handle_t *handle, bool *status) {
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assert(status);
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status_t result;
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uint32_t regValue;
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/* Read the PHY Status register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_PHYSTS_REG, &regValue);
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if (result == kStatus_Success) {
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if ((PHY_PHYSTS_LINKSTATUS_MASK & regValue) != 0U) {
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/* Link up. */
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*status = true;
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} else {
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/* Link down. */
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*status = false;
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}
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}
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return result;
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}
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status_t PHY_DP83867_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex) {
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assert(!((speed == NULL) && (duplex == NULL)));
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status_t result;
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uint32_t regValue;
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/* Read the status register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_PHYSTS_REG, &regValue);
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if (result == kStatus_Success) {
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if (speed != NULL) {
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switch ((regValue & PHY_PHYSTS_LINKSPEED_MASK) >> PHY_PHYSTS_LINKSPEED_SHIFT)
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{
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case PHY_PHYSTS_LINKSPEED_10M:
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*speed = kPHY_Speed10M;
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break;
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case PHY_PHYSTS_LINKSPEED_100M:
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*speed = kPHY_Speed100M;
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break;
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case PHY_PHYSTS_LINKSPEED_1000M:
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*speed = kPHY_Speed1000M;
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break;
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default:
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*speed = kPHY_Speed10M;
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break;
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}
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}
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if (duplex != NULL) {
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if ((regValue & PHY_PHYSTS_LINKDUPLEX_MASK) != 0U) {
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*duplex = kPHY_FullDuplex;
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} else {
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*duplex = kPHY_HalfDuplex;
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}
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}
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}
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return result;
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}
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status_t PHY_DP83867_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex) {
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status_t result;
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uint32_t regValue;
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
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if (result == kStatus_Success) {
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/* Disable the auto-negotiation and set according to user-defined configuration. */
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regValue &= ~PHY_BCTL_AUTONEG_MASK;
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if (speed == kPHY_Speed1000M) {
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regValue &= ~PHY_BCTL_SPEED0_MASK;
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regValue |= PHY_BCTL_SPEED1_MASK;
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} else if (speed == kPHY_Speed100M) {
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regValue |= PHY_BCTL_SPEED0_MASK;
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regValue &= ~PHY_BCTL_SPEED1_MASK;
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} else {
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regValue &= ~PHY_BCTL_SPEED0_MASK;
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regValue &= ~PHY_BCTL_SPEED1_MASK;
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}
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if (duplex == kPHY_FullDuplex) {
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regValue |= PHY_BCTL_DUPLEX_MASK;
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} else {
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regValue &= ~PHY_BCTL_DUPLEX_MASK;
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}
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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}
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return result;
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}
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status_t PHY_DP83867_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable) {
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/* This PHY only supports local loopback. */
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assert(mode == kPHY_LocalLoop);
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status_t result;
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uint32_t regValue;
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/* Set the loop mode. */
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if (enable) {
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if (speed == kPHY_Speed1000M) {
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regValue = PHY_BCTL_SPEED1_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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} else if (speed == kPHY_Speed100M) {
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regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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} else {
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regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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} else {
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/* First read the current status in control register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
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if (result == kStatus_Success) {
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regValue &= ~PHY_BCTL_LOOP_MASK;
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
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(regValue | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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return result;
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}

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