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Fix order of shl/shr
1 parent 5267ae3 commit d1b11a5

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3 files changed

+30
-33
lines changed

3 files changed

+30
-33
lines changed

crates/codegen/src/yul/emitter.rs

Lines changed: 26 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -346,22 +346,20 @@ impl<'db> YulEmitter<'db> {
346346
YulError::Unsupported("assignment to unknown binding".into())
347347
})?;
348348
let rhs = self.lower_value(*value, state)?;
349-
let func = match op {
350-
ArithBinOp::Add => "add",
351-
ArithBinOp::Sub => "sub",
352-
ArithBinOp::Mul => "mul",
353-
ArithBinOp::Div => "div",
354-
ArithBinOp::Rem => "mod",
355-
ArithBinOp::Pow => "exp",
356-
ArithBinOp::LShift => "shl",
357-
ArithBinOp::RShift => "shr",
358-
ArithBinOp::BitAnd => "and",
359-
ArithBinOp::BitOr => "or",
360-
ArithBinOp::BitXor => "xor",
349+
let assignment = match op {
350+
ArithBinOp::Add => format!("add({yul_name}, {rhs})"),
351+
ArithBinOp::Sub => format!("sub({yul_name}, {rhs})"),
352+
ArithBinOp::Mul => format!("mul({yul_name}, {rhs})"),
353+
ArithBinOp::Div => format!("div({yul_name}, {rhs})"),
354+
ArithBinOp::Rem => format!("mod({yul_name}, {rhs})"),
355+
ArithBinOp::Pow => format!("exp({yul_name}, {rhs})"),
356+
ArithBinOp::LShift => format!("shl({rhs}, {yul_name})"),
357+
ArithBinOp::RShift => format!("shr({rhs}, {yul_name})"),
358+
ArithBinOp::BitAnd => format!("and({yul_name}, {rhs})"),
359+
ArithBinOp::BitOr => format!("or({yul_name}, {rhs})"),
360+
ArithBinOp::BitXor => format!("xor({yul_name}, {rhs})"),
361361
};
362-
docs.push(YulDoc::line(format!(
363-
"{yul_name} := {func}({yul_name}, {rhs})"
364-
)));
362+
docs.push(YulDoc::line(format!("{yul_name} := {assignment}")));
365363
}
366364
mir::MirInst::Eval { .. } => {}
367365
}
@@ -426,20 +424,19 @@ impl<'db> YulEmitter<'db> {
426424
BinOp::Arith(op) => {
427425
let left = self.lower_expr(*lhs, state)?;
428426
let right = self.lower_expr(*rhs, state)?;
429-
let func = match op {
430-
ArithBinOp::Add => "add",
431-
ArithBinOp::Sub => "sub",
432-
ArithBinOp::Mul => "mul",
433-
ArithBinOp::Div => "div",
434-
ArithBinOp::Rem => "mod",
435-
ArithBinOp::Pow => "exp",
436-
ArithBinOp::LShift => "shl",
437-
ArithBinOp::RShift => "shr",
438-
ArithBinOp::BitAnd => "and",
439-
ArithBinOp::BitOr => "or",
440-
ArithBinOp::BitXor => "xor",
441-
};
442-
Ok(format!("{func}({left}, {right})"))
427+
match op {
428+
ArithBinOp::Add => Ok(format!("add({left}, {right})")),
429+
ArithBinOp::Sub => Ok(format!("sub({left}, {right})")),
430+
ArithBinOp::Mul => Ok(format!("mul({left}, {right})")),
431+
ArithBinOp::Div => Ok(format!("div({left}, {right})")),
432+
ArithBinOp::Rem => Ok(format!("mod({left}, {right})")),
433+
ArithBinOp::Pow => Ok(format!("exp({left}, {right})")),
434+
ArithBinOp::LShift => Ok(format!("shl({right}, {left})")),
435+
ArithBinOp::RShift => Ok(format!("shr({right}, {left})")),
436+
ArithBinOp::BitAnd => Ok(format!("and({left}, {right})")),
437+
ArithBinOp::BitOr => Ok(format!("or({left}, {right})")),
438+
ArithBinOp::BitXor => Ok(format!("xor({left}, {right})")),
439+
}
443440
}
444441
BinOp::Comp(op) => {
445442
let left = self.lower_expr(*lhs, state)?;

crates/codegen/tests/fixtures/aug_assign_bit_ops.snap

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ input_file: tests/fixtures/aug_assign_bit_ops.fe
88
function aug_assign_bit_ops(x, y) -> ret {
99
let v0 := x
1010
v0 := exp(v0, y)
11-
v0 := shl(v0, 3)
12-
v0 := shr(v0, 1)
11+
v0 := shl(3, v0)
12+
v0 := shr(1, v0)
1313
v0 := and(v0, 255)
1414
v0 := or(v0, 1)
1515
v0 := xor(v0, 2)

crates/codegen/tests/fixtures/bit_ops.snap

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ input_file: tests/fixtures/bit_ops.fe
99
let v0 := and(x, y)
1010
let v1 := or(x, y)
1111
let v2 := xor(x, y)
12-
let v3 := shl(x, 8)
13-
let v4 := shr(x, 2)
12+
let v3 := shl(8, x)
13+
let v4 := shr(2, x)
1414
ret := tuple(v0, v1, v2, v3, v4)
1515
}
1616
}

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