Skip to content

Commit fb8284c

Browse files
fhahngithub-actions[bot]
fhahn
authored and
github-actions[bot]
committed
Automerge: [VPlan] Remove original loop blocks if dead. (#155497)
Build on top of llvm/llvm-project#154510 to completely remove the blocks of dead scalar loops. Depends on llvm/llvm-project#154510. PR: llvm/llvm-project#155497
2 parents c1f84f8 + 8907b6d commit fb8284c

File tree

231 files changed

+1492
-11722
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

231 files changed

+1492
-11722
lines changed

‎llvm/lib/Transforms/Vectorize/VPlan.cpp‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -968,24 +968,26 @@ void VPlan::execute(VPTransformState *State) {
968968
// logic generic during VPlan execution.
969969
State->CFG.DTU.applyUpdates(
970970
{{DominatorTree::Delete, ScalarPh, ScalarPh->getSingleSuccessor()}});
971-
} else {
971+
}
972+
ReversePostOrderTraversal<VPBlockShallowTraversalWrapper<VPBlockBase *>> RPOT(
973+
Entry);
974+
// Generate code for the VPlan, in parts of the vector skeleton, loop body and
975+
// successor blocks including the middle, exit and scalar preheader blocks.
976+
for (VPBlockBase *Block : RPOT)
977+
Block->execute(State);
978+
979+
// If the original loop is unreachable, delete it and all its blocks.
980+
if (!ScalarPhVPBB->hasPredecessors()) {
972981
Loop *OrigLoop =
973982
State->LI->getLoopFor(getScalarHeader()->getIRBasicBlock());
974-
// If the original loop is unreachable, we need to delete it.
975983
auto Blocks = OrigLoop->getBlocksVector();
976984
Blocks.push_back(cast<VPIRBasicBlock>(ScalarPhVPBB)->getIRBasicBlock());
977985
for (auto *BB : Blocks)
978986
State->LI->removeBlock(BB);
987+
DeleteDeadBlocks(Blocks, &State->CFG.DTU);
979988
State->LI->erase(OrigLoop);
980989
}
981990

982-
ReversePostOrderTraversal<VPBlockShallowTraversalWrapper<VPBlockBase *>> RPOT(
983-
Entry);
984-
// Generate code for the VPlan, in parts of the vector skeleton, loop body and
985-
// successor blocks including the middle, exit and scalar preheader blocks.
986-
for (VPBlockBase *Block : RPOT)
987-
Block->execute(State);
988-
989991
State->CFG.DTU.flush();
990992

991993
VPBasicBlock *Header = vputils::getFirstLoopHeader(*this, State->VPDT);

‎llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll‎

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -81,17 +81,6 @@ define void @powi_call(ptr %P) {
8181
; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]
8282
; CHECK: [[MIDDLE_BLOCK]]:
8383
; CHECK-NEXT: br label %[[EXIT:.*]]
84-
; CHECK: [[SCALAR_PH:.*]]:
85-
; CHECK-NEXT: br label %[[LOOP:.*]]
86-
; CHECK: [[LOOP]]:
87-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
88-
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds double, ptr [[P]], i64 [[IV]]
89-
; CHECK-NEXT: [[L:%.*]] = load double, ptr [[GEP]], align 8
90-
; CHECK-NEXT: [[POWI:%.*]] = tail call double @llvm.powi.f64.i32(double [[L]], i32 3)
91-
; CHECK-NEXT: store double [[POWI]], ptr [[GEP]], align 8
92-
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
93-
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1
94-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]]
9584
; CHECK: [[EXIT]]:
9685
; CHECK-NEXT: ret void
9786
;

‎llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll‎

Lines changed: 0 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -33,20 +33,7 @@ define void @clamped_tc_8(ptr nocapture %dst, i32 %n, i64 %val) vscale_range(1,1
3333
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 8 x i64> [[VEC_IND]], [[DOTSPLAT]]
3434
; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
3535
; CHECK: middle.block:
36-
; CHECK-NEXT: br label [[FOR_COND_CLEANUP:%.*]]
37-
; CHECK: scalar.ph:
3836
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
39-
; CHECK: for.body:
40-
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[SCALAR_PH:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
41-
; CHECK-NEXT: [[P_OUT_TAIL_09:%.*]] = phi ptr [ [[DST]], [[SCALAR_PH]] ], [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ]
42-
; CHECK-NEXT: [[TMP19:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 3
43-
; CHECK-NEXT: [[SHR3:%.*]] = lshr i64 [[VAL]], [[TMP19]]
44-
; CHECK-NEXT: [[CONV4:%.*]] = trunc i64 [[SHR3]] to i8
45-
; CHECK-NEXT: store i8 [[CONV4]], ptr [[P_OUT_TAIL_09]], align 1
46-
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[P_OUT_TAIL_09]], i64 1
47-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
48-
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 8
49-
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
5037
; CHECK: for.cond.cleanup:
5138
; CHECK-NEXT: ret void
5239
;
@@ -108,20 +95,7 @@ define void @clamped_tc_max_8(ptr nocapture %dst, i32 %n, i64 %val) vscale_range
10895
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 8 x i64> [[VEC_IND]], [[DOTSPLAT]]
10996
; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
11097
; CHECK: middle.block:
111-
; CHECK-NEXT: br label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]]
112-
; CHECK: scalar.ph:
11398
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
114-
; CHECK: for.body:
115-
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[SCALAR_PH:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
116-
; CHECK-NEXT: [[P_OUT_TAIL_09:%.*]] = phi ptr [ [[DST]], [[SCALAR_PH]] ], [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ]
117-
; CHECK-NEXT: [[TMP19:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 3
118-
; CHECK-NEXT: [[SHR3:%.*]] = lshr i64 [[VAL]], [[TMP19]]
119-
; CHECK-NEXT: [[CONV4:%.*]] = trunc i64 [[SHR3]] to i8
120-
; CHECK-NEXT: store i8 [[CONV4]], ptr [[P_OUT_TAIL_09]], align 1
121-
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[P_OUT_TAIL_09]], i64 1
122-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
123-
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
124-
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]]
12599
; CHECK: for.cond.cleanup.loopexit:
126100
; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
127101
; CHECK: for.cond.cleanup:

‎llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll‎

Lines changed: 16 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -362,8 +362,9 @@ define void @latch_branch_cost(ptr %dst) {
362362
; PRED-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], 104
363363
; PRED-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
364364
; PRED: [[MIDDLE_BLOCK]]:
365-
; PRED-NEXT: br [[EXIT:label %.*]]
366-
; PRED: [[SCALAR_PH:.*:]]
365+
; PRED-NEXT: br label %[[EXIT:.*]]
366+
; PRED: [[EXIT]]:
367+
; PRED-NEXT: ret void
367368
;
368369
entry:
369370
br label %loop
@@ -585,8 +586,9 @@ define void @multiple_exit_conditions(ptr %src, ptr noalias %dst) #1 {
585586
; PRED-NEXT: [[TMP16:%.*]] = xor i1 [[TMP15]], true
586587
; PRED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
587588
; PRED: [[MIDDLE_BLOCK]]:
588-
; PRED-NEXT: br [[EXIT:label %.*]]
589-
; PRED: [[SCALAR_PH:.*:]]
589+
; PRED-NEXT: br label %[[EXIT:.*]]
590+
; PRED: [[EXIT]]:
591+
; PRED-NEXT: ret void
590592
;
591593
entry:
592594
br label %loop
@@ -609,7 +611,6 @@ exit:
609611
}
610612

611613
define void @low_trip_count_fold_tail_scalarized_store(ptr %dst) {
612-
;
613614
; COMMON-LABEL: define void @low_trip_count_fold_tail_scalarized_store(
614615
; COMMON-SAME: ptr [[DST:%.*]]) {
615616
; COMMON-NEXT: [[ENTRY:.*:]]
@@ -659,16 +660,16 @@ define void @low_trip_count_fold_tail_scalarized_store(ptr %dst) {
659660
; COMMON-NEXT: store i8 6, ptr [[TMP6]], align 1
660661
; COMMON-NEXT: br label %[[PRED_STORE_CONTINUE12]]
661662
; COMMON: [[PRED_STORE_CONTINUE12]]:
662-
; COMMON-NEXT: br i1 false, label %[[PRED_STORE_IF13:.*]], label %[[EXIT:.*]]
663+
; COMMON-NEXT: br i1 false, label %[[PRED_STORE_IF13:.*]], label %[[EXIT1:.*]]
663664
; COMMON: [[PRED_STORE_IF13]]:
664665
; COMMON-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[DST]], i64 7
665666
; COMMON-NEXT: store i8 7, ptr [[TMP7]], align 1
666-
; COMMON-NEXT: br label %[[EXIT]]
667-
; COMMON: [[EXIT]]:
668-
; COMMON-NEXT: br label %[[SCALAR_PH:.*]]
669-
; COMMON: [[SCALAR_PH]]:
670-
; COMMON-NEXT: br [[EXIT1:label %.*]]
671-
; COMMON: [[SCALAR_PH1:.*:]]
667+
; COMMON-NEXT: br label %[[EXIT1]]
668+
; COMMON: [[EXIT1]]:
669+
; COMMON-NEXT: br label %[[SCALAR_PH1:.*]]
670+
; COMMON: [[SCALAR_PH1]]:
671+
; COMMON-NEXT: br [[EXIT:label %.*]]
672+
; COMMON: [[SCALAR_PH:.*:]]
672673
;
673674
entry:
674675
br label %loop
@@ -1160,8 +1161,9 @@ define void @redundant_branch_and_tail_folding(ptr %dst, i1 %c) {
11601161
; PRED-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24
11611162
; PRED-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
11621163
; PRED: [[MIDDLE_BLOCK]]:
1163-
; PRED-NEXT: br [[EXIT:label %.*]]
1164-
; PRED: [[SCALAR_PH:.*:]]
1164+
; PRED-NEXT: br label %[[EXIT:.*]]
1165+
; PRED: [[EXIT]]:
1166+
; PRED-NEXT: ret void
11651167
;
11661168
entry:
11671169
br label %loop.header

‎llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll‎

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -65,36 +65,6 @@ define void @check_widen_intrinsic_with_nnan(ptr noalias %dst.0, ptr noalias %ds
6565
; CHECK-NEXT: br i1 [[TMP34]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
6666
; CHECK: [[MIDDLE_BLOCK]]:
6767
; CHECK-NEXT: br label %[[EXIT:.*]]
68-
; CHECK: [[SCALAR_PH:.*]]:
69-
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
70-
; CHECK: [[LOOP_HEADER]]:
71-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
72-
; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds double, ptr [[SRC_1]], i64 [[IV]]
73-
; CHECK-NEXT: [[L_1:%.*]] = load double, ptr [[GEP_SRC_1]], align 8
74-
; CHECK-NEXT: [[ABS:%.*]] = tail call nnan double @llvm.fabs.f64(double [[L_1]])
75-
; CHECK-NEXT: [[C_0:%.*]] = fcmp olt double [[ABS]], 1.000000e+00
76-
; CHECK-NEXT: br i1 [[C_0]], label %[[THEN:.*]], label %[[ELSE:.*]]
77-
; CHECK: [[THEN]]:
78-
; CHECK-NEXT: [[L_2:%.*]] = load double, ptr [[SRC_2]], align 8
79-
; CHECK-NEXT: [[IV_SUB_1:%.*]] = add nsw i64 [[IV]], -1
80-
; CHECK-NEXT: [[GEP_IV_SUB_1:%.*]] = getelementptr double, ptr [[DST_0]], i64 [[IV_SUB_1]]
81-
; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_IV_SUB_1]], align 8
82-
; CHECK-NEXT: [[C_1:%.*]] = fcmp oeq double [[L_2]], 0.000000e+00
83-
; CHECK-NEXT: br i1 [[C_1]], label %[[MERGE:.*]], label %[[LOOP_LATCH]]
84-
; CHECK: [[ELSE]]:
85-
; CHECK-NEXT: [[IV_SUB_2:%.*]] = add nsw i64 [[IV]], -1
86-
; CHECK-NEXT: [[GEP_IV_SUB_2:%.*]] = getelementptr double, ptr [[DST_0]], i64 [[IV_SUB_2]]
87-
; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_IV_SUB_2]], align 8
88-
; CHECK-NEXT: br label %[[MERGE]]
89-
; CHECK: [[MERGE]]:
90-
; CHECK-NEXT: [[MERGE_IV:%.*]] = phi i64 [ [[IV_SUB_2]], %[[ELSE]] ], [ [[IV_SUB_1]], %[[THEN]] ]
91-
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds i32, ptr [[DST_1]], i64 [[MERGE_IV]]
92-
; CHECK-NEXT: store i32 10, ptr [[GEP_DST_1]], align 4
93-
; CHECK-NEXT: br label %[[LOOP_LATCH]]
94-
; CHECK: [[LOOP_LATCH]]:
95-
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
96-
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1000
97-
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP_HEADER]]
9868
; CHECK: [[EXIT]]:
9969
; CHECK-NEXT: ret void
10070
;

‎llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence-fold-tail.ll‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -69,20 +69,7 @@ define i32 @test_phi_iterator_invalidation(ptr %A, ptr noalias %B) {
6969
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
7070
; CHECK-NEXT: br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
7171
; CHECK: middle.block:
72-
; CHECK-NEXT: br label [[EXIT:%.*]]
73-
; CHECK: scalar.ph:
7472
; CHECK-NEXT: br label [[LOOP:%.*]]
75-
; CHECK: loop:
76-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[SCALAR_PH:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
77-
; CHECK-NEXT: [[SCALAR_RECUR:%.*]] = phi i16 [ 0, [[SCALAR_PH]] ], [ [[FOR_NEXT:%.*]], [[LOOP]] ]
78-
; CHECK-NEXT: [[SEXT:%.*]] = sext i16 [[SCALAR_RECUR]] to i32
79-
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
80-
; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV_NEXT]]
81-
; CHECK-NEXT: [[FOR_NEXT]] = load i16, ptr [[GEP_A]], align 2
82-
; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr i32, ptr [[B]], i64 [[IV_NEXT]]
83-
; CHECK-NEXT: store i32 [[SEXT]], ptr [[GEP_B]], align 4
84-
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1001
85-
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]]
8673
; CHECK: exit:
8774
; CHECK-NEXT: ret i32 0
8875
;

‎llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll‎

Lines changed: 1 addition & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -18,21 +18,8 @@ define double @test_reduction_costs() {
1818
; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
1919
; CHECK: [[MIDDLE_BLOCK]]:
2020
; CHECK-NEXT: br label %[[EXIT:.*]]
21-
; CHECK: [[SCALAR_PH:.*]]:
22-
; CHECK-NEXT: br label %[[LOOP_1:.*]]
23-
; CHECK: [[LOOP_1]]:
24-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_1]] ]
25-
; CHECK-NEXT: [[R_1:%.*]] = phi double [ 0.000000e+00, %[[SCALAR_PH]] ], [ [[R_1_NEXT:%.*]], %[[LOOP_1]] ]
26-
; CHECK-NEXT: [[R_2:%.*]] = phi double [ 0.000000e+00, %[[SCALAR_PH]] ], [ [[R_2_NEXT:%.*]], %[[LOOP_1]] ]
27-
; CHECK-NEXT: [[R_1_NEXT]] = fadd double [[R_1]], 3.000000e+00
28-
; CHECK-NEXT: [[R_2_NEXT]] = fadd double [[R_2]], 9.000000e+00
29-
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
30-
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1
31-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_1]]
3221
; CHECK: [[EXIT]]:
33-
; CHECK-NEXT: [[R_1_NEXT_LCSSA:%.*]] = phi double [ [[R_1_NEXT]], %[[LOOP_1]] ], [ [[TMP0]], %[[MIDDLE_BLOCK]] ]
34-
; CHECK-NEXT: [[R_2_NEXT_LCSSA:%.*]] = phi double [ [[R_2_NEXT]], %[[LOOP_1]] ], [ [[TMP1]], %[[MIDDLE_BLOCK]] ]
35-
; CHECK-NEXT: [[DIV:%.*]] = fmul double [[R_1_NEXT_LCSSA]], [[R_2_NEXT_LCSSA]]
22+
; CHECK-NEXT: [[DIV:%.*]] = fmul double [[TMP0]], [[TMP1]]
3623
; CHECK-NEXT: ret double [[DIV]]
3724
;
3825
entry:

‎llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll‎

Lines changed: 1 addition & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -169,22 +169,9 @@ define i64 @int_and_pointer_iv(ptr %start, i32 %N) {
169169
; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
170170
; CHECK: middle.block:
171171
; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP5]], i32 2
172-
; CHECK-NEXT: br label [[EXIT:%.*]]
173-
; CHECK: scalar.ph:
174172
; CHECK-NEXT: br label [[LOOP:%.*]]
175-
; CHECK: loop:
176-
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[SCALAR_PH:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
177-
; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP]] ]
178-
; CHECK-NEXT: [[SCALAR_RECUR:%.*]] = phi i64 [ 0, [[SCALAR_PH]] ], [ [[RECUR_NEXT:%.*]], [[LOOP]] ]
179-
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[PTR_IV]], align 4
180-
; CHECK-NEXT: [[RECUR_NEXT]] = zext i32 [[L]] to i64
181-
; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 4
182-
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
183-
; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 1000
184-
; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[EXIT]], label [[LOOP]]
185173
; CHECK: exit:
186-
; CHECK-NEXT: [[RECUR_LCSSA:%.*]] = phi i64 [ [[SCALAR_RECUR]], [[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], [[MIDDLE_BLOCK]] ]
187-
; CHECK-NEXT: ret i64 [[RECUR_LCSSA]]
174+
; CHECK-NEXT: ret i64 [[VECTOR_RECUR_EXTRACT_FOR_PHI]]
188175
;
189176
entry:
190177
br label %loop

‎llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -51,22 +51,8 @@ define i32 @test_invariant_replicate_region(i32 %x, i1 %c) {
5151
; CHECK: [[MIDDLE_BLOCK]]:
5252
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3
5353
; CHECK-NEXT: br label %[[EXIT:.*]]
54-
; CHECK: [[SCALAR_PH:.*]]:
55-
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
56-
; CHECK: [[LOOP_HEADER]]:
57-
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
58-
; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
59-
; CHECK: [[THEN]]:
60-
; CHECK-NEXT: [[REM_1:%.*]] = urem i32 10, [[X]]
61-
; CHECK-NEXT: br label %[[LOOP_LATCH]]
62-
; CHECK: [[LOOP_LATCH]]:
63-
; CHECK-NEXT: [[RES:%.*]] = phi i32 [ 0, %[[LOOP_HEADER]] ], [ [[REM_1]], %[[THEN]] ]
64-
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
65-
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV]], 99
66-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]]
6754
; CHECK: [[EXIT]]:
68-
; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi i32 [ [[RES]], %[[LOOP_LATCH]] ], [ [[TMP17]], %[[MIDDLE_BLOCK]] ]
69-
; CHECK-NEXT: ret i32 [[RES_LCSSA]]
55+
; CHECK-NEXT: ret i32 [[TMP17]]
7056
;
7157
entry:
7258
br label %loop.header

‎llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -474,19 +474,8 @@ define i32 @tc4(ptr noundef readonly captures(none) %tmp) vscale_range(1,16) {
474474
; CHECK: [[MIDDLE_BLOCK]]:
475475
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])
476476
; CHECK-NEXT: br label %[[EXIT:.*]]
477-
; CHECK: [[SCALAR_PH:.*]]:
478-
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
479-
; CHECK: [[FOR_BODY]]:
480-
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
481-
; CHECK-NEXT: [[SUM_0179:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
482-
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP]], i64 [[INDVARS_IV]]
483-
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
484-
; CHECK-NEXT: [[ADD]] = add i32 [[SUM_0179]], [[TMP5]]
485-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
486-
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4
487477
; CHECK: [[EXIT]]:
488-
; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP4]], %[[MIDDLE_BLOCK]] ]
489-
; CHECK-NEXT: ret i32 [[ADD_LCSSA]]
478+
; CHECK-NEXT: ret i32 [[TMP4]]
490479
;
491480
entry:
492481
br label %for.body
@@ -520,6 +509,7 @@ define i32 @tc4_from_profile(ptr noundef readonly captures(none) %tmp, i64 %N) v
520509
; CHECK-NEXT: [[ADD]] = add i32 [[SUM_0179]], [[TMP0]]
521510
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
522511
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]]
512+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]], !prof [[PROF9:![0-9]+]]
523513
; CHECK: [[EXIT]]:
524514
; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], %[[FOR_BODY]] ]
525515
; CHECK-NEXT: ret i32 [[ADD_LCSSA]]

0 commit comments

Comments
 (0)