Pipelined Design?

[fantasysee]

Hi, Jon.
Thanks for your open-source FPU design. Amazing!
Having read the Verilog code of computation unit, I was impressive of the computational flow by a finite state machine.
However, I am wondering how to insert pipeline into your FPU design, for the sake of improving its throughput? The problem has puzzled me for almost half months. I wanna figure out how to insert pipeline in a finite state machine. Is it accessible? Wish for your help. Thank you.

[dawsonjon]

Hi, Thanks very much for your interest in my project, and thanks also for your kind words. If you wanted to pipeline the design, then I would recommend breaking the state machine down into several smaller state machines running concurrently, each would perform a small part of the process before handing the data off to the next state machine in the pipeline for further processing. There would be a trade-off however, in order to achieve the higher throughput you would need much more area. A division for example is computed a bit at a time over many cycles using a single subtractor and shifter. If you wanted to improve the throughput rate of the divider to allow one calculation per clock cycle you would need to use dozens of subtractors/shifters. If you are interested in trying to get the best possible performance from floating point units you could take a look at one of my other projects https://github.com/dawsonjon/verilog-math. This project doesn't have much in the way of documentation, but I have used some python scripts to help me design an efficient pipeline. I have implemented fully pipelined versions of all the most common floating point units. The units can achieve a throughput rate of one calculation per clock cycle, and can achieve a reasonable clock speed in FPGA. Thanks Jon

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On Sun, 2 Jun 2019 at 17:16, fantasysee ***@***.***> wrote: Hi, Jon. Thanks for your open-source FPU design. Amazing! Having read the Verilog code of computation unit, I was impressive of the computational flow by a finite state machine. However, I am wondering *how to insert pipeline into your FPU design, for the sake of improving its throughput?* The problem has puzzled me for almost half months. I wanna figure out how to insert pipeline in a finite state machine. Is it accessible? Wish for your help. Thank you. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#17?email_source=notifications&email_token=AAFPFXZBK6LFPR2OFO2RZ4LPYPWZ7A5CNFSM4HSC7II2YY3PNVWWK3TUL52HS4DFUVEXG43VMWVGG33NNVSW45C7NFSM4GXE4QAA>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AAFPFXYNDPDPKOTXR26KEA3PYPWZ7ANCNFSM4HSC7IIQ> .

[fantasysee]

@dawsonjon Thank you very much for your kind reply!!! I really learned a lot. I will follow the project you recommended. Thanks for your advice.