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i509VCBi509VCB
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Merge pull request #4770 from i509VCB/lpc55-uart-alt-fn
nxp/lpc55: move usart ALT pin definitions to impl_xx_pin macros
2 parents 2a79c55 + da5a563 commit 2800889

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+88
-52
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‎embassy-nxp/CHANGELOG.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
77

88
<!-- next-header -->
99
## Unreleased - ReleaseDate
10+
- LPC55: Move ALT definitions for USART to TX/RX pin impls.
1011
- LPC55: Remove internal match_iocon macro
1112
- LPC55: DMA Controller and asynchronous version of USART
1213
- Moved NXP LPC55S69 from `lpc55-pac` to `nxp-pac`

‎embassy-nxp/src/usart/lpc55.rs‎

Lines changed: 87 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,8 @@ impl<'d, M: Mode> UsartTx<'d, M> {
146146
tx_dma: Peri<'d, impl Channel>,
147147
config: Config,
148148
) -> Self {
149-
Usart::<M>::init::<T>(Some(tx.into()), None, config);
149+
let tx_func = tx.pin_func();
150+
Usart::<M>::init::<T>(Some((tx.into(), tx_func)), None, config);
150151
Self::new_inner(T::info(), Some(tx_dma.into()))
151152
}
152153

@@ -179,7 +180,8 @@ impl<'d, M: Mode> UsartTx<'d, M> {
179180

180181
impl<'d> UsartTx<'d, Blocking> {
181182
pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
182-
Usart::<Blocking>::init::<T>(Some(tx.into()), None, config);
183+
let tx_func = tx.pin_func();
184+
Usart::<Blocking>::init::<T>(Some((tx.into(), tx_func)), None, config);
183185
Self::new_inner(T::info(), None)
184186
}
185187
}
@@ -208,7 +210,8 @@ impl<'d, M: Mode> UsartRx<'d, M> {
208210
rx_dma: Peri<'d, impl Channel>,
209211
config: Config,
210212
) -> Self {
211-
Usart::<M>::init::<T>(None, Some(rx.into()), config);
213+
let rx_func = rx.pin_func();
214+
Usart::<M>::init::<T>(None, Some((rx.into(), rx_func)), config);
212215
Self::new_inner(T::info(), T::dma_state(), has_irq, Some(rx_dma.into()))
213216
}
214217

@@ -280,7 +283,8 @@ impl<'d, M: Mode> UsartRx<'d, M> {
280283

281284
impl<'d> UsartRx<'d, Blocking> {
282285
pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
283-
Usart::<Blocking>::init::<T>(None, Some(rx.into()), config);
286+
let rx_func = rx.pin_func();
287+
Usart::<Blocking>::init::<T>(None, Some((rx.into(), rx_func)), config);
284288
Self::new_inner(T::info(), T::dma_state(), false, None)
285289
}
286290
}
@@ -405,7 +409,10 @@ impl<'d> Usart<'d, Blocking> {
405409
rx: Peri<'d, impl RxPin<T>>,
406410
config: Config,
407411
) -> Self {
408-
Self::new_inner(usart, tx.into(), rx.into(), false, None, None, config)
412+
let tx_func = tx.pin_func();
413+
let rx_func = rx.pin_func();
414+
415+
Self::new_inner(usart, tx.into(), tx_func, rx.into(), rx_func, false, None, None, config)
409416
}
410417
}
411418

@@ -419,10 +426,15 @@ impl<'d> Usart<'d, Async> {
419426
rx_dma: Peri<'d, impl RxChannel<T>>,
420427
config: Config,
421428
) -> Self {
429+
let tx_func = tx.pin_func();
430+
let rx_func = rx.pin_func();
431+
422432
Self::new_inner(
423433
uart,
424434
tx.into(),
435+
tx_func,
425436
rx.into(),
437+
rx_func,
426438
true,
427439
Some(tx_dma.into()),
428440
Some(rx_dma.into()),
@@ -435,20 +447,26 @@ impl<'d, M: Mode> Usart<'d, M> {
435447
fn new_inner<T: Instance>(
436448
_usart: Peri<'d, T>,
437449
mut tx: Peri<'d, AnyPin>,
450+
tx_func: PioFunc,
438451
mut rx: Peri<'d, AnyPin>,
452+
rx_func: PioFunc,
439453
has_irq: bool,
440454
tx_dma: Option<Peri<'d, AnyChannel>>,
441455
rx_dma: Option<Peri<'d, AnyChannel>>,
442456
config: Config,
443457
) -> Self {
444-
Self::init::<T>(Some(tx.reborrow()), Some(rx.reborrow()), config);
458+
Self::init::<T>(Some((tx.reborrow(), tx_func)), Some((rx.reborrow(), rx_func)), config);
445459
Self {
446460
tx: UsartTx::new_inner(T::info(), tx_dma),
447461
rx: UsartRx::new_inner(T::info(), T::dma_state(), has_irq, rx_dma),
448462
}
449463
}
450464

451-
fn init<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>, config: Config) {
465+
fn init<T: Instance>(
466+
tx: Option<(Peri<'_, AnyPin>, PioFunc)>,
467+
rx: Option<(Peri<'_, AnyPin>, PioFunc)>,
468+
config: Config,
469+
) {
452470
Self::configure_flexcomm(T::info().fc_reg, T::instance_number());
453471
Self::configure_clock::<T>(&config);
454472
Self::pin_config::<T>(tx, rx);
@@ -553,10 +571,10 @@ impl<'d, M: Mode> Usart<'d, M> {
553571
.modify(|w| w.set_brgval((brg_value - 1) as u16));
554572
}
555573

556-
fn pin_config<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>) {
557-
if let Some(tx_pin) = tx {
574+
fn pin_config<T: Instance>(tx: Option<(Peri<'_, AnyPin>, PioFunc)>, rx: Option<(Peri<'_, AnyPin>, PioFunc)>) {
575+
if let Some((tx_pin, func)) = tx {
558576
tx_pin.pio().modify(|w| {
559-
w.set_func(T::tx_pin_func());
577+
w.set_func(func);
560578
w.set_mode(iocon::vals::PioMode::INACTIVE);
561579
w.set_slew(iocon::vals::PioSlew::STANDARD);
562580
w.set_invert(false);
@@ -565,9 +583,9 @@ impl<'d, M: Mode> Usart<'d, M> {
565583
});
566584
}
567585

568-
if let Some(rx_pin) = rx {
586+
if let Some((rx_pin, func)) = rx {
569587
rx_pin.pio().modify(|w| {
570-
w.set_func(T::rx_pin_func());
588+
w.set_func(func);
571589
w.set_mode(iocon::vals::PioMode::INACTIVE);
572590
w.set_slew(iocon::vals::PioSlew::STANDARD);
573591
w.set_invert(false);
@@ -810,8 +828,6 @@ trait SealedInstance {
810828
fn info() -> &'static Info;
811829
fn dma_state() -> &'static DmaState;
812830
fn instance_number() -> usize;
813-
fn tx_pin_func() -> PioFunc;
814-
fn rx_pin_func() -> PioFunc;
815831
}
816832

817833
/// UART instance.
@@ -822,7 +838,7 @@ pub trait Instance: SealedInstance + PeripheralType {
822838
}
823839

824840
macro_rules! impl_instance {
825-
($inst:ident, $fc:ident, $tx_pin:ident, $rx_pin:ident, $fc_num:expr) => {
841+
($inst:ident, $fc:ident, $fc_num:expr) => {
826842
impl $crate::usart::inner::SealedInstance for $crate::peripherals::$inst {
827843
fn info() -> &'static Info {
828844
static INFO: Info = Info {
@@ -844,60 +860,79 @@ macro_rules! impl_instance {
844860
fn instance_number() -> usize {
845861
$fc_num
846862
}
847-
#[inline]
848-
fn tx_pin_func() -> PioFunc {
849-
PioFunc::$tx_pin
850-
}
851-
#[inline]
852-
fn rx_pin_func() -> PioFunc {
853-
PioFunc::$rx_pin
854-
}
855863
}
856864
impl $crate::usart::Instance for $crate::peripherals::$inst {
857865
type Interrupt = crate::interrupt::typelevel::$fc;
858866
}
859867
};
860868
}
861869

862-
impl_instance!(USART0, FLEXCOMM0, ALT1, ALT1, 0);
863-
impl_instance!(USART1, FLEXCOMM1, ALT2, ALT2, 1);
864-
impl_instance!(USART2, FLEXCOMM2, ALT1, ALT1, 2);
865-
impl_instance!(USART3, FLEXCOMM3, ALT1, ALT1, 3);
866-
impl_instance!(USART4, FLEXCOMM4, ALT1, ALT2, 4);
867-
impl_instance!(USART5, FLEXCOMM5, ALT3, ALT3, 5);
868-
impl_instance!(USART6, FLEXCOMM6, ALT2, ALT2, 6);
869-
impl_instance!(USART7, FLEXCOMM7, ALT7, ALT7, 7);
870+
impl_instance!(USART0, FLEXCOMM0, 0);
871+
impl_instance!(USART1, FLEXCOMM1, 1);
872+
impl_instance!(USART2, FLEXCOMM2, 2);
873+
impl_instance!(USART3, FLEXCOMM3, 3);
874+
impl_instance!(USART4, FLEXCOMM4, 4);
875+
impl_instance!(USART5, FLEXCOMM5, 5);
876+
impl_instance!(USART6, FLEXCOMM6, 6);
877+
impl_instance!(USART7, FLEXCOMM7, 7);
878+
879+
pub(crate) trait SealedTxPin<T: Instance>: crate::gpio::Pin {
880+
fn pin_func(&self) -> PioFunc;
881+
}
882+
883+
pub(crate) trait SealedRxPin<T: Instance>: crate::gpio::Pin {
884+
fn pin_func(&self) -> PioFunc;
885+
}
870886

871887
/// Trait for TX pins.
872-
pub trait TxPin<T: Instance>: crate::gpio::Pin {}
888+
#[allow(private_bounds)]
889+
pub trait TxPin<T: Instance>: SealedTxPin<T> + crate::gpio::Pin {}
890+
873891
/// Trait for RX pins.
874-
pub trait RxPin<T: Instance>: crate::gpio::Pin {}
892+
#[allow(private_bounds)]
893+
pub trait RxPin<T: Instance>: SealedRxPin<T> + crate::gpio::Pin {}
894+
895+
macro_rules! impl_tx_pin {
896+
($pin:ident, $instance:ident, $func: ident) => {
897+
impl SealedTxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
898+
fn pin_func(&self) -> PioFunc {
899+
PioFunc::$func
900+
}
901+
}
875902

876-
macro_rules! impl_pin {
877-
($pin:ident, $instance:ident, Tx) => {
878903
impl TxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
879904
};
880-
($pin:ident, $instance:ident, Rx) => {
905+
}
906+
907+
macro_rules! impl_rx_pin {
908+
($pin:ident, $instance:ident, $func: ident) => {
909+
impl SealedRxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
910+
fn pin_func(&self) -> PioFunc {
911+
PioFunc::$func
912+
}
913+
}
914+
881915
impl RxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
882916
};
883917
}
884918

885-
impl_pin!(PIO1_6, USART0, Tx);
886-
impl_pin!(PIO1_5, USART0, Rx);
887-
impl_pin!(PIO1_11, USART1, Tx);
888-
impl_pin!(PIO1_10, USART1, Rx);
889-
impl_pin!(PIO0_27, USART2, Tx);
890-
impl_pin!(PIO1_24, USART2, Rx);
891-
impl_pin!(PIO0_2, USART3, Tx);
892-
impl_pin!(PIO0_3, USART3, Rx);
893-
impl_pin!(PIO0_16, USART4, Tx);
894-
impl_pin!(PIO0_5, USART4, Rx);
895-
impl_pin!(PIO0_9, USART5, Tx);
896-
impl_pin!(PIO0_8, USART5, Rx);
897-
impl_pin!(PIO1_16, USART6, Tx);
898-
impl_pin!(PIO1_13, USART6, Rx);
899-
impl_pin!(PIO0_19, USART7, Tx);
900-
impl_pin!(PIO0_20, USART7, Rx);
919+
impl_tx_pin!(PIO1_6, USART0, ALT1);
920+
impl_tx_pin!(PIO1_11, USART1, ALT2);
921+
impl_tx_pin!(PIO0_27, USART2, ALT1);
922+
impl_tx_pin!(PIO0_2, USART3, ALT1);
923+
impl_tx_pin!(PIO0_16, USART4, ALT1);
924+
impl_tx_pin!(PIO0_9, USART5, ALT3);
925+
impl_tx_pin!(PIO1_16, USART6, ALT2);
926+
impl_tx_pin!(PIO0_19, USART7, ALT7);
927+
928+
impl_rx_pin!(PIO1_5, USART0, ALT1);
929+
impl_rx_pin!(PIO1_10, USART1, ALT2);
930+
impl_rx_pin!(PIO1_24, USART2, ALT1);
931+
impl_rx_pin!(PIO0_3, USART3, ALT1);
932+
impl_rx_pin!(PIO0_5, USART4, ALT2);
933+
impl_rx_pin!(PIO0_8, USART5, ALT3);
934+
impl_rx_pin!(PIO1_13, USART6, ALT2);
935+
impl_rx_pin!(PIO0_20, USART7, ALT7);
901936

902937
/// Trait for TX DMA channels.
903938
pub trait TxChannel<T: Instance>: crate::dma::Channel {}

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