stm32/ADC: Fix prescaler calculation to include MAX frequency.

Due to the integer rounding rules one has to subtract 1 from the numerator.
For example:

Let max clock be 55 and supplied clock be 110
110/55 = 2 which results in the divider being set to 4 and the clock after division ends up being 27 instead of 55
Subtracting 1 to the numerator get around the rounding issue
109/55 = 1 which results in the divider being set to 2 and the clock after division ends up being 55 which is exactly max clock

Author: esden

embassy-stm32/CHANGELOG.md

@@ -31,6 +31,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: stm32/usart: add `eager_reads` option to control if buffered readers return as soon as possible or after more data is available ([#4668](https://github.com/embassy-rs/embassy/pull/4668))
 - feat: stm32/usart: add `de_assertion_time` and `de_deassertion_time` config options
 - change: stm32/uart: BufferedUartRx now returns all available bytes from the internal buffer
+- fix: Calculate the ADC prescaler in a way that it allows for the max frequency to be reached
 
 ## 0.4.0 - 2025-08-26
 

embassy-stm32/src/adc/adc4.rs

@@ -128,7 +128,8 @@ enum Prescaler {
 
 impl Prescaler {
     fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        // Calculate prescaler in a way where the clock can hit MAX CLK
+        let raw_prescaler = frequency.0.saturating_sub(1) / MAX_ADC_CLK_FREQ.0;
         match raw_prescaler {
             0 => Self::NotDivided,
             1 => Self::DividedBy2,

embassy-stm32/src/adc/c0.rs

@@ -66,7 +66,8 @@ pub enum Prescaler {
 
 impl Prescaler {
     fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        // Calculate prescaler in a way where the clock can hit MAX CLK
+        let raw_prescaler = frequency.0.saturating_sub(1) / MAX_ADC_CLK_FREQ.0;
         match raw_prescaler {
             0 => Self::NotDivided,
             1 => Self::DividedBy2,

embassy-stm32/src/adc/g4.rs

@@ -72,7 +72,8 @@ enum Prescaler {
 
 impl Prescaler {
     fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        // Calculate prescaler in a way where the clock can hit MAX CLK
+        let raw_prescaler = frequency.0.saturating_sub(1) / MAX_ADC_CLK_FREQ.0;
         match raw_prescaler {
             0 => Self::NotDivided,
             1 => Self::DividedBy2,

embassy-stm32/src/adc/v2.rs

@@ -71,7 +71,8 @@ impl Prescaler {
         // Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz.
         #[cfg(not(stm32f2))]
         const MAX_FREQUENCY: Hertz = Hertz(36_000_000);
-        let raw_div = freq.0 / MAX_FREQUENCY.0;
+        // Calculate prescaler divider including MAX_FREQ
+        let raw_div = freq.0.saturating_sub(1) / MAX_FREQUENCY.0;
         match raw_div {
             0..=1 => Self::Div2,
             2..=3 => Self::Div4,

embassy-stm32/src/adc/v4.rs

@@ -93,7 +93,8 @@ enum Prescaler {
 
 impl Prescaler {
     fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        // Calculate prescaler in a way where the clock can hit MAX CLK
+        let raw_prescaler = frequency.0.saturating_sub(1) / MAX_ADC_CLK_FREQ.0;
         match raw_prescaler {
             0 => Self::NotDivided,
             1 => Self::DividedBy2,