STM32 Async I2C4 BDMA error. Need help with memory.x configuration. #4936
Description
Hello I have been trying to use the Async I2C4 Master peripheral on an STM32H723GZ MCU. Every time I run the firmware I get a DMA panic on the BDMA peripheral. I2C4 can only be used with BDMA instead of DMA due to how the chip is designed. This does not happen if I use the other I2Cs with the regular DMA. I made sure to setup the clocks correctly by using CubeMX to verify the clock setup.
My code:
#![no_std]
#![no_main]
mod fmt;
#[cfg(feature = "defmt")]
use {defmt_rtt as _, panic_probe as _};
use embassy_executor::Spawner;
use embassy_stm32::{
Peri, bind_interrupts,
gpio::{AnyPin, Level, Output, Speed},
i2c,
i2c::{Config, I2c},
peripherals,
time::Hertz,
};
use embassy_time::Timer;
use fmt::info;
use scd30_interface::asynch::Scd30;
use scd30_interface::data::DataStatus;
bind_interrupts!(struct Irqs {
I2C4_EV => i2c::EventInterruptHandler<peripherals::I2C4>;
I2C4_ER => i2c::ErrorInterruptHandler<peripherals::I2C4>;
});
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut peripheral_config = embassy_stm32::Config::default();
{
use embassy_stm32::rcc::*;
peripheral_config.rcc.hse = Some(Hse {
freq: Hertz::mhz(25),
mode: HseMode::Oscillator,
});
peripheral_config.rcc.pll1 = Some(Pll {
source: PllSource::HSE,
prediv: PllPreDiv::DIV2, // 12.5MHz needs to be between 1 to 16 MHz
mul: PllMul::MUL32,
divp: Some(PllDiv::DIV1), // 400 MHz system clock
divq: Some(PllDiv::DIV2), // 200 MHz
divr: Some(PllDiv::DIV2), // 200 MHz
});
peripheral_config.rcc.pll2 = Some(Pll {
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
mul: PllMul::MUL32,
divp: Some(PllDiv::DIV2), // 200MHz
divq: Some(PllDiv::DIV2),
divr: Some(PllDiv::DIV2),
});
peripheral_config.rcc.sys = Sysclk::PLL1_P;
peripheral_config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 MHz
peripheral_config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 MHz
peripheral_config.rcc.apb2_pre = APBPrescaler::DIV2;
peripheral_config.rcc.apb3_pre = APBPrescaler::DIV2;
peripheral_config.rcc.apb4_pre = APBPrescaler::DIV2;
peripheral_config.rcc.mux.i2c4sel = mux::I2c4sel::PCLK4; // 100 MHz
peripheral_config.rcc.mux.i2c1235sel = mux::I2c1235sel::PCLK1;
peripheral_config.rcc.mux.sdmmcsel = mux::Sdmmcsel::PLL2_R; // 200 MHz
peripheral_config.rcc.supply_config = SupplyConfig::LDO;
peripheral_config.rcc.voltage_scale = VoltageScale::Scale0;
}
let p = embassy_stm32::init(peripheral_config);
let mut i2c_config = Config::default();
i2c_config.frequency = Hertz::khz(50);
i2c_config.timeout = Duration::from_millis(100);
let i2c4 = I2c::new(
p.I2C4,
p.PD12, // scl
p.PD13, // sda
Irqs,
p.BDMA1_CH0,
p.BDMA1_CH1,
i2c_config,
);
let mut scd30_sensor = Scd30::new(i2c1);
let version = scd30_sensor.read_firmware_version().await;
if version.is_err() {
info!("Unable to get version!");
}
let version = version.unwrap();
info!("SCD30 version: {}.{}", version.major, version.minor);
loop {
while scd30_sensor.is_data_ready().await.unwrap() != DataStatus::Ready {
Timer::after_millis(10).await;
}
let measurement = scd30_sensor.read_measurement().await.unwrap();
info!(
"Co2: {}ppm, Temp: {}C, Hum: {}%RH",
measurement.co2_concentration, measurement.temperature, measurement.humidity
);
Timer::after_millis(500).await;
}
}
My memory.x file is based on the example for stm32h723 with the change to line 61 to use AXISRAM as the main ram region:
MEMORY
{
/* This file is intended for parts in the STM32H723 family. (RM0468) */
/* - FLASH and RAM are mandatory memory sections. */
/* - The sum of all non-FLASH sections must add to 564k total device RAM. */
/* - The FLASH section size must match your device, see table below. */
/* FLASH */
/* Select the appropriate FLASH size for your device. */
/* - STM32H730xB 128K */
/* - STM32H723xE/725xE 512K */
/* - STM32H723xG/725xG/733xG/735xG 1M */
FLASH1 : ORIGIN = 0x08000000, LENGTH = 1M
/* Data TCM */
/* - Two contiguous 64KB RAMs. */
/* - Used for interrupt handlers, stacks and general RAM. */
/* - Zero wait-states. */
/* - The DTCM is taken as the origin of the base ram. (See below.) */
/* This is also where the interrupt table and such will live, */
/* which is required for deterministic performance. */
DTCM : ORIGIN = 0x20000000, LENGTH = 128K
/* Instruction TCM */
/* - More memory can be assigned to ITCM. See AXI SRAM notes, below. */
/* - Used for latency-critical interrupt handlers etc. */
/* - Zero wait-states. */
ITCM : ORIGIN = 0x00000000, LENGTH = 64K + 0K
/* AXI SRAM */
/* - AXISRAM is in D1 and accessible by all system masters except BDMA. */
/* - Suitable for application data not stored in DTCM. */
/* - Zero wait-states. */
/* - The 192k of extra shared RAM is fully allotted to the AXI SRAM by default. */
/* As a result: 64k (64k + 0k) for ITCM and 320k (128k + 192k) for AXI SRAM. */
/* This can be re-configured via the TCM_AXI_SHARED[1,0] register when more */
/* ITCM is required. */
AXISRAM : ORIGIN = 0x24000000, LENGTH = 128K + 192K
/* AHB SRAM */
/* - SRAM1-2 are in D2 and accessible by all system masters except BDMA, LTDC */
/* and SDMMC1. Suitable for use as DMA buffers. */
/* - SRAM4 is in D3 and additionally accessible by the BDMA. Used for BDMA */
/* buffers, for storing application data in lower-power modes. */
/* - Zero wait-states. */
SRAM1 : ORIGIN = 0x30000000, LENGTH = 16K
SRAM2 : ORIGIN = 0x30040000, LENGTH = 16K
SRAM4 : ORIGIN = 0x38000000, LENGTH = 16K
/* Backup SRAM */
/* Used to store data during low-power sleeps. */
BSRAM : ORIGIN = 0x38800000, LENGTH = 4K
}
/*
/* Assign the memory regions defined above for use. */
/*
/* Provide the mandatory FLASH and RAM definitions for cortex-m-rt's linker script. */
REGION_ALIAS(FLASH, FLASH1);
REGION_ALIAS(RAM, AXISRAM);
/* The location of the stack can be overridden using the `_stack_start` symbol. */
/* - Set the stack location at the end of RAM, using all remaining space. */
_stack_start = ORIGIN(RAM) + LENGTH(RAM);
/* The location of the .text section can be overridden using the */
/* `_stext` symbol. By default it will place after .vector_table. */
/* _stext = ORIGIN(FLASH) + 0x40c; */
/* Define sections for placing symbols into the extra memory regions above. */
/* This makes them accessible from code. */
/* - ITCM, DTCM and AXISRAM connect to a 64-bit wide bus -> align to 8 bytes. */
/* - All other memories connect to a 32-bit wide bus -> align to 4 bytes. */
SECTIONS {
.itcm (NOLOAD) : ALIGN(8) {
*(.itcm .itcm.*);
. = ALIGN(8);
} > ITCM
.axisram (NOLOAD) : ALIGN(8) {
*(.axisram .axisram.*);
. = ALIGN(8);
} > AXISRAM
.sram1 (NOLOAD) : ALIGN(4) {
*(.sram1 .sram1.*);
. = ALIGN(4);
} > SRAM1
.sram2 (NOLOAD) : ALIGN(4) {
*(.sram2 .sram2.*);
. = ALIGN(4);
} > SRAM2
.sram4 (NOLOAD) : ALIGN(4) {
*(.sram4 .sram4.*);
. = ALIGN(4);
} > SRAM4
.bsram (NOLOAD) : ALIGN(4) {
*(.bsram .bsram.*);
. = ALIGN(4);
} > BSRAM
};
I think something needs to be done in memory.x since BDMA can only write to SRAM4.