Expose SIMD registers as a possible register class in asm macros

[Dominaezzz]

I want to be able to write this

#[derive(Copy, Clone, Default)]
#[repr(align(16))]
#[repr(simd)]
pub struct u8x16([u8; 16]);

let a = u8x16([1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]);
let mut dest = a;

unsafe {
    asm!(
        "EE.VADDS.S8 {dst}, {dst}, {rhs}",
        dst = inout(qreg) dest,
        rhs = in(qreg) a,
    );
}

instead of this

#[derive(Copy, Clone, Default)]
#[repr(align(16))]
#[repr(simd)]
pub struct u8x16([u8; 16]);

let a = u8x16([1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]);
let mut dest = a;

unsafe {
    asm!(
        "EE.VLD.128.IP q0, {dst}, 0",
        "EE.VLD.128.IP q1, {rhs}, 0",
        "EE.VADDS.S8 {dst}, {dst}, {rhs}",
        "EE.VST.128.IP q0, {dst}, 0",
        dst = in(reg) &mut dest.0,
        rhs = in(reg) &a.0,
    );
}

This allows me not not have to choose specific registers and leave that to the compiler.
It also leaves the job of loading/storing from/to memory to the compiler, which means will allow it to only do it when necessary, as suppose to me doing it for every single operation.
The compiler would be smart enough to recycle registers and the values in them for further operations.
Also: If the compiler/llvm auto-vectorizes for loops to use SIMD, manual register choices in asm! may conflict with the registers chosen by optimiser.

From what I see, a qreg (name pending bike-shed) register class needs adding here:

• https://github.com/esp-rs/rust/blob/esp-1.90.0.0/compiler/rustc_target/src/asm/xtensa.rs#L8
• https://github.com/esp-rs/rust/blob/esp-1.90.0.0/compiler/rustc_target/src/asm/xtensa.rs#L153
• https://github.com/espressif/llvm-project/blob/release/esp_20.x/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td#L75-L84 (already added?)

I haven't figured out how to teach Rustland or LLVM about the special load and store instructions for the 128 bit registers.
I'm also not sure what to add here https://github.com/esp-rs/rust/blob/esp-1.90.0.0/compiler/rustc_target/src/asm/xtensa.rs#L43, will likely have to look upstream to see how they inject "simd types" in there.