Add WidthCast operation to VAST.

Examples: 14'(42), MyWidth'(x), (MyWidth+1)'(100)

Author: meheff

xls/codegen/vast/vast.cc

@@ -672,6 +672,46 @@ std::string ModulePort::ToString() const {
                          xls::verilog::ToString(direction), name());
 }
 
+static bool IsDigitsOrIdentifier(std::string_view s) {
+  if (s.empty()) {
+    return false;
+  }
+
+  bool all_digits = true;
+  for (char ch : s) {
+    if (!absl::ascii_isdigit(ch)) {
+      all_digits = false;
+      break;
+    }
+  }
+  if (all_digits) {
+    return true;
+  }
+
+  const char first = s.front();
+  if (!absl::ascii_isalpha(first) && first != '_') {
+    return false;
+  }
+  for (char ch : s.substr(1)) {
+    if (!absl::ascii_isalnum(ch) && ch != '_') {
+      return false;
+    }
+  }
+  return true;
+}
+
+std::string WidthCast::Emit(LineInfo* line_info) const {
+  LineInfoStart(line_info, this);
+  LineInfoEnd(line_info, this);
+  std::string width_expr = width_->Emit(line_info);
+  if (IsDigitsOrIdentifier(width_expr)) {
+    // Parentheses are not needed for digits or identifiers.
+    return absl::StrFormat("%s'(%s)", width_expr, value_->Emit(line_info));
+  } else {
+    return absl::StrFormat("(%s)'(%s)", width_expr, value_->Emit(line_info));
+  }
+}
+
 VerilogFunction::VerilogFunction(std::string_view name, DataType* result_type,
                                  VerilogFile* file, const SourceInfo& loc)
     : VastNode(file, loc),

xls/codegen/vast/vast.h

@@ -2159,6 +2159,26 @@ class UnsignedCast final : public SystemFunctionCall {
       : SystemFunctionCall("unsigned", {value}, file, loc) {}
 };
 
+// A SystemVerilog cast-to-width expression. Examples:
+//   17'(42)
+//   MyParam'(MyOtherParam + 2)
+//   (MyParam + 1)'(x)
+class WidthCast final : public Expression {
+ public:
+  WidthCast(Expression* width, Expression* value, VerilogFile* file,
+            const SourceInfo& loc)
+      : Expression(file, loc), width_(width), value_(value) {}
+
+  std::string Emit(LineInfo* line_info) const final;
+
+  Expression* width() const { return width_; }
+  Expression* value() const { return value_; }
+
+ private:
+  Expression* width_;
+  Expression* value_;
+};
+
 // Represents the definition of a Verilog function.
 class VerilogFunction final : public VastNode {
  public:

xls/codegen/vast/vast_test.cc

@@ -1740,6 +1740,55 @@ TEST_P(VastTest, SignedOperation) {
 endmodule)");
 }
 
+TEST_P(VastTest, WidthCastEmission) {
+  const SourceInfo si;
+  VerilogFile f(GetFileType());
+  Module* m = f.AddModule("top", si);
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * a,
+                           m->AddInput("a", f.BitVectorType(8, si), si));
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * b,
+                           m->AddInput("b", f.BitVectorType(4, si), si));
+  XLS_ASSERT_OK_AND_ASSIGN(
+      LogicRef * out_literal,
+      m->AddOutput("out_literal", f.BitVectorType(8, si), si));
+  XLS_ASSERT_OK_AND_ASSIGN(
+      LogicRef * out_param,
+      m->AddOutput("out_param", f.BitVectorType(12, si), si));
+  XLS_ASSERT_OK_AND_ASSIGN(
+      LogicRef * out_expr,
+      m->AddOutput("out_expr", f.BitVectorType(16, si), si));
+
+  ParameterRef* width_param =
+      m->AddParameter("WidthParam", f.PlainLiteral(12, si), si);
+
+  m->Add<ContinuousAssignment>(
+      si, out_literal,
+      f.Make<WidthCast>(si, f.PlainLiteral(8, si),
+                        f.Add(a, f.PlainLiteral(1, si), si)));
+  m->Add<ContinuousAssignment>(
+      si, out_param, f.Make<WidthCast>(si, width_param, f.Concat({a, b}, si)));
+
+  Expression* complex_width = f.Add(width_param, f.PlainLiteral(4, si), si);
+  Expression* complex_value =
+      f.BitwiseXor(a, f.Concat({b, f.Literal(3, 2, si)}, si), si);
+  m->Add<ContinuousAssignment>(
+      si, out_expr, f.Make<WidthCast>(si, complex_width, complex_value));
+
+  EXPECT_EQ(m->Emit(nullptr),
+            R"(module top(
+  input wire [7:0] a,
+  input wire [3:0] b,
+  output wire [7:0] out_literal,
+  output wire [11:0] out_param,
+  output wire [15:0] out_expr
+);
+  parameter WidthParam = 12;
+  assign out_literal = 8'(a + 1);
+  assign out_param = WidthParam'({a, b});
+  assign out_expr = (WidthParam + 4)'(a ^ {b, 2'h3});
+endmodule)");
+}
+
 TEST_P(VastTest, ComplexConditional) {
   VerilogFile f(GetFileType());
   Module* m = f.AddModule("top", SourceInfo());

xls/public/c_api_symbols.txt

@@ -350,6 +350,7 @@ xls_vast_verilog_file_make_unary
 xls_vast_verilog_file_make_unsized_one_literal
 xls_vast_verilog_file_make_unsized_x_literal
 xls_vast_verilog_file_make_unsized_zero_literal
+xls_vast_verilog_file_make_width_cast
 xls_vast_verilog_module_add_always_at
 xls_vast_verilog_module_add_always_ff
 xls_vast_verilog_module_add_input

xls/public/c_api_vast.cc

@@ -605,6 +605,17 @@ struct xls_vast_expression* xls_vast_verilog_file_make_ternary(
   return reinterpret_cast<xls_vast_expression*>(result);
 }
 
+struct xls_vast_expression* xls_vast_verilog_file_make_width_cast(
+    struct xls_vast_verilog_file* f, struct xls_vast_expression* width,
+    struct xls_vast_expression* value) {
+  auto* cpp_file = reinterpret_cast<xls::verilog::VerilogFile*>(f);
+  auto* cpp_width = reinterpret_cast<xls::verilog::Expression*>(width);
+  auto* cpp_value = reinterpret_cast<xls::verilog::Expression*>(value);
+  xls::verilog::Expression* result = cpp_file->Make<xls::verilog::WidthCast>(
+      xls::SourceInfo(), cpp_width, cpp_value);
+  return reinterpret_cast<xls_vast_expression*>(result);
+}
+
 struct xls_vast_concat* xls_vast_verilog_file_make_concat(
     struct xls_vast_verilog_file* f, struct xls_vast_expression** elements,
     size_t element_count) {

xls/public/c_api_vast.h

@@ -298,6 +298,10 @@ struct xls_vast_expression* xls_vast_verilog_file_make_ternary(
     struct xls_vast_expression* consequent,
     struct xls_vast_expression* alternate);
 
+struct xls_vast_expression* xls_vast_verilog_file_make_width_cast(
+    struct xls_vast_verilog_file* f, struct xls_vast_expression* width,
+    struct xls_vast_expression* value);
+
 struct xls_vast_index* xls_vast_verilog_file_make_index_i64(
     struct xls_vast_verilog_file* f,
     struct xls_vast_indexable_expression* subject, int64_t index);

xls/public/c_api_vast_test.cc

@@ -389,6 +389,147 @@ endmodule
   EXPECT_EQ(std::string_view{emitted}, kWantEmitted);
 }
 
+TEST(XlsCApiTest, VastWidthCast) {
+  const std::string_view kWantEmitted = R"(module top(
+  input wire [7:0] a,
+  input wire [3:0] b,
+  output wire [7:0] out_literal,
+  output wire [11:0] out_param,
+  output wire [15:0] out_expr
+);
+  parameter WidthParam = 12;
+  assign out_literal = 8'(a + 1);
+  assign out_param = WidthParam'({a, b});
+  assign out_expr = (WidthParam + 4)'(a ^ {b, 2'h3});
+endmodule
+)";
+
+  xls_vast_verilog_file* f =
+      xls_vast_make_verilog_file(xls_vast_file_type_verilog);
+  ASSERT_NE(f, nullptr);
+  absl::Cleanup free_file([&] { xls_vast_verilog_file_free(f); });
+
+  xls_vast_verilog_module* m = xls_vast_verilog_file_add_module(f, "top");
+  ASSERT_NE(m, nullptr);
+
+  xls_vast_data_type* u8 =
+      xls_vast_verilog_file_make_bit_vector_type(f, 8, /*is_signed=*/false);
+  xls_vast_data_type* u4 =
+      xls_vast_verilog_file_make_bit_vector_type(f, 4, /*is_signed=*/false);
+  xls_vast_data_type* u12 =
+      xls_vast_verilog_file_make_bit_vector_type(f, 12, /*is_signed=*/false);
+  xls_vast_data_type* u16 =
+      xls_vast_verilog_file_make_bit_vector_type(f, 16, /*is_signed=*/false);
+
+  xls_vast_logic_ref* a_ref = xls_vast_verilog_module_add_input(m, "a", u8);
+  ASSERT_NE(a_ref, nullptr);
+  xls_vast_logic_ref* b_ref = xls_vast_verilog_module_add_input(m, "b", u4);
+  ASSERT_NE(b_ref, nullptr);
+  xls_vast_logic_ref* out_literal_ref =
+      xls_vast_verilog_module_add_output(m, "out_literal", u8);
+  ASSERT_NE(out_literal_ref, nullptr);
+  xls_vast_logic_ref* out_param_ref =
+      xls_vast_verilog_module_add_output(m, "out_param", u12);
+  ASSERT_NE(out_param_ref, nullptr);
+  xls_vast_logic_ref* out_expr_ref =
+      xls_vast_verilog_module_add_output(m, "out_expr", u16);
+  ASSERT_NE(out_expr_ref, nullptr);
+
+  xls_vast_literal* literal_12 =
+      xls_vast_verilog_file_make_plain_literal(f, 12);
+  ASSERT_NE(literal_12, nullptr);
+  xls_vast_parameter_ref* width_param = xls_vast_verilog_module_add_parameter(
+      m, "WidthParam", xls_vast_literal_as_expression(literal_12));
+  ASSERT_NE(width_param, nullptr);
+  xls_vast_expression* width_param_expr =
+      xls_vast_parameter_ref_as_expression(width_param);
+
+  xls_vast_literal* literal_8 = xls_vast_verilog_file_make_plain_literal(f, 8);
+  ASSERT_NE(literal_8, nullptr);
+  xls_vast_literal* literal_1 = xls_vast_verilog_file_make_plain_literal(f, 1);
+  ASSERT_NE(literal_1, nullptr);
+  xls_vast_expression* a_expr = xls_vast_logic_ref_as_expression(a_ref);
+  ASSERT_NE(a_expr, nullptr);
+  xls_vast_expression* a_plus_one = xls_vast_verilog_file_make_binary(
+      f, a_expr, xls_vast_literal_as_expression(literal_1),
+      xls_vast_operator_kind_add);
+  ASSERT_NE(a_plus_one, nullptr);
+
+  xls_vast_expression* width_cast_literal =
+      xls_vast_verilog_file_make_width_cast(
+          f, xls_vast_literal_as_expression(literal_8), a_plus_one);
+  ASSERT_NE(width_cast_literal, nullptr);
+  xls_vast_continuous_assignment* assign_literal =
+      xls_vast_verilog_file_make_continuous_assignment(
+          f, xls_vast_logic_ref_as_expression(out_literal_ref),
+          width_cast_literal);
+  ASSERT_NE(assign_literal, nullptr);
+  xls_vast_verilog_module_add_member_continuous_assignment(m, assign_literal);
+
+  std::vector<xls_vast_expression*> param_concat_args = {
+      xls_vast_logic_ref_as_expression(a_ref),
+      xls_vast_logic_ref_as_expression(b_ref)};
+  xls_vast_concat* param_concat = xls_vast_verilog_file_make_concat(
+      f, param_concat_args.data(), param_concat_args.size());
+  ASSERT_NE(param_concat, nullptr);
+  xls_vast_expression* width_cast_param = xls_vast_verilog_file_make_width_cast(
+      f, width_param_expr, xls_vast_concat_as_expression(param_concat));
+  ASSERT_NE(width_cast_param, nullptr);
+  xls_vast_continuous_assignment* assign_param =
+      xls_vast_verilog_file_make_continuous_assignment(
+          f, xls_vast_logic_ref_as_expression(out_param_ref), width_cast_param);
+  ASSERT_NE(assign_param, nullptr);
+  xls_vast_verilog_module_add_member_continuous_assignment(m, assign_param);
+
+  xls_vast_literal* literal_4 = xls_vast_verilog_file_make_plain_literal(f, 4);
+  ASSERT_NE(literal_4, nullptr);
+  xls_vast_expression* complex_width = xls_vast_verilog_file_make_binary(
+      f, width_param_expr, xls_vast_literal_as_expression(literal_4),
+      xls_vast_operator_kind_add);
+  ASSERT_NE(complex_width, nullptr);
+
+  struct xls_bits* bits = nullptr;
+  char* error_out = nullptr;
+  ASSERT_TRUE(
+      xls_bits_make_ubits(/*bit_count=*/2, /*value=*/3, &error_out, &bits));
+  ASSERT_EQ(error_out, nullptr);
+  absl::Cleanup free_bits([&] { xls_bits_free(bits); });
+
+  xls_vast_literal* literal_2h3 = nullptr;
+  ASSERT_TRUE(xls_vast_verilog_file_make_literal(
+      f, bits, xls_format_preference_hex, /*emit_bit_count=*/true, &error_out,
+      &literal_2h3));
+  ASSERT_EQ(error_out, nullptr);
+  ASSERT_NE(literal_2h3, nullptr);
+
+  std::vector<xls_vast_expression*> tail_concat_args = {
+      xls_vast_logic_ref_as_expression(b_ref),
+      xls_vast_literal_as_expression(literal_2h3)};
+  xls_vast_concat* tail_concat = xls_vast_verilog_file_make_concat(
+      f, tail_concat_args.data(), tail_concat_args.size());
+  ASSERT_NE(tail_concat, nullptr);
+
+  xls_vast_expression* complex_value = xls_vast_verilog_file_make_binary(
+      f, a_expr, xls_vast_concat_as_expression(tail_concat),
+      xls_vast_operator_kind_bitwise_xor);
+  ASSERT_NE(complex_value, nullptr);
+
+  xls_vast_expression* width_cast_complex =
+      xls_vast_verilog_file_make_width_cast(f, complex_width, complex_value);
+  ASSERT_NE(width_cast_complex, nullptr);
+  xls_vast_continuous_assignment* assign_complex =
+      xls_vast_verilog_file_make_continuous_assignment(
+          f, xls_vast_logic_ref_as_expression(out_expr_ref),
+          width_cast_complex);
+  ASSERT_NE(assign_complex, nullptr);
+  xls_vast_verilog_module_add_member_continuous_assignment(m, assign_complex);
+
+  char* emitted = xls_vast_verilog_file_emit(f);
+  ASSERT_NE(emitted, nullptr);
+  absl::Cleanup free_emitted([&] { xls_c_str_free(emitted); });
+  EXPECT_EQ(std::string_view{emitted}, kWantEmitted);
+}
+
 TEST(XlsCApiTest, VastUnsizedLiteralsParameters) {
   const std::string_view kWantEmitted = R"(module top;
   parameter P0 = '0;