[enhancement] Preserve all trace log levels in generated Verilog

[rw1nkler]

What's hard to do? (limit 100 words)

The trace log levels from DSLX are not kept in the generated Verilog. Because of this, every time you want to change the log level for simulation, you need to regenerate the design.

Right now, the TraceVerbosityPass in codegen removes traces that don’t match the log level set via max_trace_verbosity codegen option. As a consequence, the final SystemVerilog only has a subset of the original logs.

It would be more flexible if all logs were preserved, so the log level could be controlled directly during simulation.

Current best alternative workaround (limit 100 words)

Change the value of max_trace_verbosity codegen option, regenerate the design, and simulate it again

Your view of the "best case XLS enhancement" (limit 100 words)

To get similar flexibility in SystemVerilog and allow changing the log level during simulation without modifying the generated code, the toolchain could use simple macros instead of directly generating $display calls. The default verbosity level could be set using a define.

For example:

`define VERBOSITY 0

`define LOG(level, msg) \
  if (`VERBOSITY >= level) $display("%s", msg);

This approach could let the toolchain adjust verbosity at simulation time by overriding the VERBOSITY define.

[rw1nkler]

It is also possible to use plusargs wrapped in ifndef SYNTHESIS blocks, so the simulator does not need to recompile the design. This approach could complement or even replace the macro + define solution.