Clone relevant sifive/freedom

sifive/freedom commit id cloned is 3624eff.

Author: borancar

.gitignore

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+/builds
+
+# sbt directories
+/target
+/project/target

.gitmodules

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+[submodule "rocket-chip"]
+	path = rocket-chip
+	url = https://github.com/ucb-bar/rocket-chip.git

LICENSE

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+
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+   Copyright 2016 SiFive, Inc.
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Makefile.e300artydevkit

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+# See LICENSE for license details.
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+BUILD_DIR := $(base_dir)/builds/e300artydevkit
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
+MODEL := E300ArtyDevKitFPGAChip
+PROJECT := sifive.freedom.everywhere.e300artydevkit
+export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
+export CONFIG := E300ArtyDevKitConfig
+export BOARD := arty
+export BOOTROM_DIR := $(base_dir)/bootrom/xip
+
+rocketchip_dir := $(base_dir)/rocket-chip
+sifiveblocks_dir := $(base_dir)/sifive-blocks
+VSRCS := \
+	$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
+	$(sifiveblocks_dir)/vsrc/SRLatch.v \
+	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
+
+include common.mk

bootrom/xip/Makefile

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+# RISCV environment variable must be set
+
+CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
+OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
+CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g
+LFLAGS=-static -nostdlib
+
+dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb
+$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts
+	dtc -I dts -O dtb -o $@ $<
+
+.PHONY: dtb
+dtb: $(dtb)
+
+elf := $(BUILD_DIR)/xip.elf
+$(elf): xip.S $(dtb)
+	$(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $<
+
+.PHONY: elf
+elf: $(elf)
+
+bin := $(BUILD_DIR)/xip.bin
+$(bin): $(elf)
+	$(OBJCOPY) -O binary $< $@
+
+.PHONY: bin
+bin: $(bin)
+
+hex := $(BUILD_DIR)/xip.hex
+$(hex): $(bin)
+	od -t x4 -An -w4 -v $< > $@
+
+.PHONY: hex
+hex: $(hex)
+
+romgen := $(BUILD_DIR)/rom.v
+$(romgen): $(hex)
+	$(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@
+
+.PHONY: romgen
+romgen: $(romgen)
+
+.PHONY: clean
+clean::
+	rm -rf $(hex) $(elf) 

bootrom/xip/xip.S

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+// See LICENSE for license details.
+// Execute in place
+// Jump directly to XIP_TARGET_ADDR
+
+  .section .text.init
+  .option norvc
+  .globl _start
+_start:
+  csrr a0, mhartid
+  la a1, dtb
+  li t0, XIP_TARGET_ADDR
+  jr t0
+
+  .section .rodata
+dtb:
+  .incbin DEVICE_TREE

build.sbt

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+// See LICENSE for license details.
+organization := "com.sifive"
+name := "freedom"
+version := "0.1.0"
+
+lazy val commonSettings = Seq(
+  scalaVersion := "2.12.4",  // This needs to match rocket-chip's scalaVersion
+  scalacOptions ++= Seq(
+    "-deprecation",
+    "-feature",
+    "-unchecked",
+    "-Xsource:2.11",
+    "-language:reflectiveCalls"
+  )
+)
+
+// A RootProject (not well-documented) tells sbt to treat the target directory
+// as its own root project, reading its build settings. If we instead used the
+// normal `project in file()` declaration, sbt would ignore all of rocket-chip's
+// build settings, and therefore not understand that it has its own dependencies
+// on chisel, etc.
+lazy val rocketChip = RootProject(file("rocket-chip"))
+
+lazy val sifiveBlocks = (project in file("sifive-blocks")).
+  dependsOn(rocketChip).
+  settings(commonSettings: _*)
+
+lazy val nvdlaBlocks = (project in file("nvidia-dla-blocks")).
+  dependsOn(rocketChip).
+  settings(commonSettings: _*)
+
+lazy val fpgaShells = (project in file("fpga-shells")).
+  dependsOn(rocketChip, sifiveBlocks).
+  settings(commonSettings: _*)
+
+lazy val freedomPlatforms = (project in file(".")).
+  dependsOn(rocketChip, sifiveBlocks, nvdlaBlocks, fpgaShells).
+  settings(commonSettings: _*)