Modify E300 to X300

Modifications:
- Increase clock to 65 MHz
- Enable user mode
- Increase HW breakpoints to 8
- Add 2 perf counters, hpmcounter3 and hpmcounter4
- Add Xilinx EthernetLite core for Arty
- Make icache 4-way set associative
- Map ITIM at 0x0800_0000
- Expand DTIM to 64k
- Add 3 local interrupts and map GPIO BTN0-BTN2 to them
- Add temporary PMOD JA remaps for robotic arm

Author: borancar

Makefile.x300artydevkit

@@ -1,11 +1,12 @@
 # See LICENSE for license details.
+# Modifications copyright (C) 2019 Hex-Five
 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
-BUILD_DIR := $(base_dir)/builds/e300artydevkit
+BUILD_DIR := $(base_dir)/builds/x300artydevkit
 FPGA_DIR := $(base_dir)/fpga-shells/xilinx
-MODEL := E300ArtyDevKitFPGAChip
-PROJECT := sifive.freedom.everywhere.e300artydevkit
-export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
-export CONFIG := E300ArtyDevKitConfig
+MODEL := X300ArtyDevKitFPGAChip
+PROJECT := hexfive.x300artydevkit
+export CONFIG_PROJECT := hexfive.x300artydevkit
+export CONFIG := X300ArtyDevKitConfig
 export BOARD := arty
 export BOOTROM_DIR := $(base_dir)/bootrom/xip
 

README.md

@@ -0,0 +1,73 @@
+# X300
+
+This repository contains the X300, a modified version of [SiFive's Freedom E300
+Platform](https://github.com/sifive/freedom/tree/3624efff1819e52cec30c72f9085158189f8b53f)
+to support [MultiZone](https://hex-five.com/products/) and IoT applications.
+Here's a comparison between the E300 and the X300:
+
+| E300             | X300                                         |
+| ---------------- | -------------------------------------------- |
+| RV32ACIM         | RV32ACIMU                                    |
+| 32.5 MHz clock   | 65 MHz clock                                 |
+| 2 HW breakpoints | 8 HW breakpoints                             |
+| no Ethernet core | Xilinx EthernetLite Ethernet core            |
+| 1-way icache     | 4-way icache                                 |
+| no ITIM          | ITIM at 0x0800\_0000                         |
+| 16 kB DTIM       | 64 kB DTIM                                   |
+| no perf counters | 2 perf counters, hpmcounter3 and hpmcounter4 |
+| no CLICs         | 3 CLICs (BTN0, BTN1 and BTN2)                |
+
+Like the Freedom E300 Arty FPGA Dev Kit, the X300 is designed to be mapped onto
+an [Arty FPGA Evaluation
+Kit](https://www.xilinx.com/products/boards-and-kits/arty.html).
+
+### Bootrom
+
+The default bootrom consists of a program that immediately jumps to address
+0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
+board.
+
+## Requirements
+
+### Vivado 2017.1 (or later)
+
+You'll need Vivado to synthesize the bistream for the Arty FPGA. You should
+have received a single node license and instructions how to install Vivado with
+your Arty FPGA Dev Kit.
+
+### RISC-V Toolchain
+
+To compile the bootloader for the X300, the RISC-V software toolchain must be
+installed locally and the $(RISCV) environment variable must point to the
+location of where the RISC-V toolchains are installed. We recommend you build
+the toolchain yourself from
+[riscv/riscv-gnu-toolchain](https://github.com/riscv/riscv-gnu-toolchain/tree/411d1345507e5313c3575720f128be9e6c0ed941)
+
+Run the following commands to clone the repository and get started:
+
+```sh
+$ git clone https://github.com/hex-five/multizone-fpga.git
+$ cd multizone-fpga
+$ git submodule update --init --recursive
+```
+
+## Building
+
+To compile the bistream, run
+
+```sh
+$ make -f Makefile.x300artydevkit mcs
+```
+
+These will place the files under `builds/x300artydevkit/obj`.
+
+Note that in order to run the `mcs` target, you need to have the `vivado`
+executable on your `PATH`.
+
+## Running
+
+For instructions for getting the generated image onto an FPGA and programming
+it with software using the [Freedom E
+SDK](https://github.com/sifive/freedom-e-sdk), please see the [Freedom E310
+Arty FPGA Dev Kit Getting Started
+Guide](https://www.sifive.com/documentation/freedom-soc/freedom-e300-arty-fpga-dev-kit-getting-started-guide/).

build.sbt

@@ -1,6 +1,7 @@
 // See LICENSE for license details.
-organization := "com.sifive"
-name := "freedom"
+// Modifications copyright (C) 2019 Hex-Five
+organization := "com.hex-five"
+name := "x300"
 version := "0.1.0"
 
 lazy val commonSettings = Seq(
@@ -25,14 +26,10 @@ lazy val sifiveBlocks = (project in file("sifive-blocks")).
   dependsOn(rocketChip).
   settings(commonSettings: _*)
 
-lazy val nvdlaBlocks = (project in file("nvidia-dla-blocks")).
-  dependsOn(rocketChip).
-  settings(commonSettings: _*)
-
 lazy val fpgaShells = (project in file("fpga-shells")).
   dependsOn(rocketChip, sifiveBlocks).
   settings(commonSettings: _*)
 
-lazy val freedomPlatforms = (project in file(".")).
-  dependsOn(rocketChip, sifiveBlocks, nvdlaBlocks, fpgaShells).
+lazy val x300 = (project in file(".")).
+  dependsOn(rocketChip, sifiveBlocks, fpgaShells).
   settings(commonSettings: _*)

fpga-shells/src/main/scala/devices/xilinx/xilinxethernetlite/XilinxEthernetLite.scala

@@ -0,0 +1,41 @@
+// See LICENSE for license details.
+// Copyright (C) 2018-2019 Hex-Five
+package sifive.fpgashells.devices.xilinx.xilinxethernetlite
+
+import Chisel._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.subsystem.{CrossesToOnlyOneClockDomain, CacheBlockBytes}
+import sifive.fpgashells.ip.xilinx.ethernetlite.{EthernetLite, PhyPort, MdioPort}
+
+class XilinxEthernetLite(implicit p: Parameters, val crossing: ClockCrossingType = NoCrossing)
+  extends LazyModule with CrossesToOnlyOneClockDomain
+{
+  val ethernetlite = LazyModule(new EthernetLite)
+
+  val slave: TLInwardNode =
+    (ethernetlite.slave
+      := AXI4Buffer()
+      := AXI4UserYanker()
+      := AXI4Deinterleaver(p(CacheBlockBytes))
+      := AXI4IdIndexer(idBits=1)
+      := TLToAXI4(adapterName = Some("ethernetlite")))
+
+  val intnode: IntOutwardNode = ethernetlite.intnode
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = IO(new Bundle {
+      val port = new Bundle with PhyPort
+                            with MdioPort {
+      }
+    })
+
+    ethernetlite.module.io.clockreset.s_axi_aclk := clock
+    ethernetlite.module.io.clockreset.s_axi_aresetn := ~reset
+
+    io.port <> ethernetlite.module.io.port
+  }
+}

fpga-shells/src/main/scala/devices/xilinx/xilinxethernetlite/XilinxEthernetLitePeriphery.scala

@@ -0,0 +1,25 @@
+// See LICENSE for license details.
+// Copyright (C) 2018-2019 Hex-Five
+package sifive.fpgashells.devices.xilinx.xilinxethernetlite
+
+import Chisel._
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts.IntSyncCrossingSink
+
+import sifive.fpgashells.ip.xilinx.ethernetlite.{PhyPort, MdioPort}
+
+trait HasSystemXilinxEthernetLite { this: BaseSubsystem =>
+  val xilinxethernetlite = LazyModule(new XilinxEthernetLite)
+  private val cname = "xilinxethernetlite"
+  sbus.coupleTo(s"slave_named_$cname") { xilinxethernetlite.crossTLIn(xilinxethernetlite.slave) :*= TLWidthWidget(sbus.beatBytes) :*= _ }
+  ibus.fromSync := xilinxethernetlite.crossIntOut(xilinxethernetlite.intnode)
+}
+
+trait HasSystemXilinxEthernetLiteModuleImp extends LazyModuleImp {
+  val outer: HasSystemXilinxEthernetLite
+  val phy = IO(new Bundle with PhyPort with MdioPort {})
+
+  phy <> outer.xilinxethernetlite.module.io.port
+}

fpga-shells/src/main/scala/ip/xilinx/Xilinx.scala

@@ -1,4 +1,5 @@
 // See LICENSE for license details.
+// Modifications copyright (C) 2018-2019 Hex-Five
 package sifive.fpgashells.ip.xilinx
 
 import Chisel._
@@ -25,6 +26,7 @@ class mmcm extends BlackBox {
     val clk_out1 = Output(Clock())
     val clk_out2 = Output(Clock())
     val clk_out3 = Output(Clock())
+    val clk_out4 = Output(Clock())
     val resetn   = Input(Bool())
     val locked   = Output(Bool())
   }