|
18 | 18 |
|
19 | 19 | #if defined(SOC_XMC7200D_E272K8384AA) |
20 | 20 | #define __IFX_PORT_MAX 35u |
| 21 | +#elif defined(SOC_XMC7100D_F144K4160AA) |
| 22 | +#define __IFX_PORT_MAX 33u |
21 | 23 | #else |
22 | 24 | #define __IFX_PORT_MAX 14u |
23 | 25 | #endif |
@@ -70,6 +72,25 @@ static struct pin_irq_map pin_irq_map[] = |
70 | 72 | {CYHAL_PORT_33, ioss_interrupts_gpio_33_IRQn}, |
71 | 73 | {CYHAL_PORT_34, ioss_interrupts_gpio_34_IRQn}, |
72 | 74 | #endif |
| 75 | +#if defined(SOC_XMC7100D_F144K4160AA) |
| 76 | + {CYHAL_PORT_15, ioss_interrupts_gpio_15_IRQn}, |
| 77 | + {CYHAL_PORT_16, ioss_interrupts_gpio_16_IRQn}, |
| 78 | + {CYHAL_PORT_17, ioss_interrupts_gpio_17_IRQn}, |
| 79 | + {CYHAL_PORT_18, ioss_interrupts_gpio_18_IRQn}, |
| 80 | + {CYHAL_PORT_19, ioss_interrupts_gpio_19_IRQn}, |
| 81 | + {CYHAL_PORT_20, ioss_interrupts_gpio_20_IRQn}, |
| 82 | + {CYHAL_PORT_21, ioss_interrupts_gpio_21_IRQn}, |
| 83 | + {CYHAL_PORT_22, ioss_interrupts_gpio_23_IRQn}, |
| 84 | + {CYHAL_PORT_24, ioss_interrupts_gpio_24_IRQn}, |
| 85 | + {CYHAL_PORT_25, ioss_interrupts_gpio_25_IRQn}, |
| 86 | + {CYHAL_PORT_26, ioss_interrupts_gpio_26_IRQn}, |
| 87 | + {CYHAL_PORT_27, ioss_interrupts_gpio_27_IRQn}, |
| 88 | + {CYHAL_PORT_28, ioss_interrupts_gpio_28_IRQn}, |
| 89 | + {CYHAL_PORT_29, ioss_interrupts_gpio_29_IRQn}, |
| 90 | + {CYHAL_PORT_30, ioss_interrupts_gpio_30_IRQn}, |
| 91 | + {CYHAL_PORT_31, ioss_interrupts_gpio_31_IRQn}, |
| 92 | + {CYHAL_PORT_32, ioss_interrupts_gpio_32_IRQn}, |
| 93 | +#endif |
73 | 94 | }; |
74 | 95 |
|
75 | 96 | static struct rt_pin_irq_hdr pin_irq_handler_tab[] = |
@@ -111,6 +132,25 @@ static struct rt_pin_irq_hdr pin_irq_handler_tab[] = |
111 | 132 | {-1, 0, RT_NULL, RT_NULL}, |
112 | 133 | {-1, 0, RT_NULL, RT_NULL}, |
113 | 134 | #endif |
| 135 | +#if defined(SOC_XMC7100D_F144K4160AA) |
| 136 | + {-1, 0, RT_NULL, RT_NULL}, |
| 137 | + {-1, 0, RT_NULL, RT_NULL}, |
| 138 | + {-1, 0, RT_NULL, RT_NULL}, |
| 139 | + {-1, 0, RT_NULL, RT_NULL}, |
| 140 | + {-1, 0, RT_NULL, RT_NULL}, |
| 141 | + {-1, 0, RT_NULL, RT_NULL}, |
| 142 | + {-1, 0, RT_NULL, RT_NULL}, |
| 143 | + {-1, 0, RT_NULL, RT_NULL}, |
| 144 | + {-1, 0, RT_NULL, RT_NULL}, |
| 145 | + {-1, 0, RT_NULL, RT_NULL}, |
| 146 | + {-1, 0, RT_NULL, RT_NULL}, |
| 147 | + {-1, 0, RT_NULL, RT_NULL}, |
| 148 | + {-1, 0, RT_NULL, RT_NULL}, |
| 149 | + {-1, 0, RT_NULL, RT_NULL}, |
| 150 | + {-1, 0, RT_NULL, RT_NULL}, |
| 151 | + {-1, 0, RT_NULL, RT_NULL}, |
| 152 | + {-1, 0, RT_NULL, RT_NULL}, |
| 153 | +#endif |
114 | 154 | }; |
115 | 155 |
|
116 | 156 | rt_inline void pin_irq_handler(int irqno) |
@@ -320,7 +360,7 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin, |
320 | 360 |
|
321 | 361 | irqmap = &pin_irq_map[gpio_port]; |
322 | 362 |
|
323 | | -#if !defined(COMPONENT_CAT1C) |
| 363 | +#if !defined(COMPONENT_CAT1C)||defined(SOC_XMC7100D_F144K4160AA) |
324 | 364 | IRQn_Type irqn = irqmap->irqno; |
325 | 365 | irq_cb_data[irqn].callback = irq_callback; |
326 | 366 | irq_cb_data[irqn].callback_arg = (rt_uint16_t *)&pin_irq_map[gpio_port].port; |
@@ -356,7 +396,7 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin, |
356 | 396 |
|
357 | 397 | irqmap = &pin_irq_map[gpio_port]; |
358 | 398 |
|
359 | | -#if !defined(COMPONENT_CAT1C) |
| 399 | +#if !defined(COMPONENT_CAT1C)||defined(SOC_XMC7100D_F144K4160AA) |
360 | 400 | IRQn_Type irqn = irqmap->irqno; |
361 | 401 | if (irqn < 0 || irqn >= PIN_IFXPORT_MAX) |
362 | 402 | { |
|
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