Similar Projects

Open source architectures or simulators that are focused on parallel processing.

Harmonica 2 SIMT processor

Multithreaded SIMT processor written in CHDL, a C++ library that outputs Verilog. Designed for use with 3D stacked DRAM.

• Status: low activity
• Instruction Set: Custom
• License: BSD
• Synthesizable: Yes

Paper
Source Repository

Miaow GPGPU

GPGPU processor from team at University of Madison-Wisconsin.

Home Page
Source Repository

• Status: low activity
• Instruction Set: AMD Southern Islands
• License: BSD
• Synthesizable: Yes

Open Piton

Manycore processor from team at Princeton. Core is based on OpenSPARC T1, but this replaces the crossbar switch and shared L2 cache of the former with a scalable 2D mesh network-on-chip.

Home Page

• Status: active
• Instruction Set: SPARC
• License: GPLv2
• Synthesizable: Yes

OpTiMSoC

Tiled multicore SoC component library from Munich Technical University (Technische Universität München (TUM)). The modular design allows combining other IP libraries and processor cores.

Home Page
Source Repository

• Status: Active
• Instruction Set: multiple, currently OpenRISC.
• License: MIT
• Synthesizable: Yes

GPGPU Sim

Cycle-accurate compute core simulator based on NVidia architecture by team at University of British Columbia. Executes NVidia PTX intermediate code.

Home Page
Source Repository

• Status: Last change was 2 years ago
• Instruction Set: NVidia PTX
• License: BSD
• Synthesizable: No

Simty

Synthesizable General-Purpose SIMT Processor. Supports hardware multithreading. Uses RISC-V (32I) instruction set.

Paper
Source Repository

• Status: Inactive (?)
• Instruction Set: RISC-V 32i (integer only)
• License: None
• Synthesizable: Yes

OpenShader

Simulator and Verilog compute core with a custom instruction set.

Source Repository

• Status: Inactive
• Instruction Set: Custom
• License: ?
• Synthesizable: Yes