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        Jeff Bush edited this page Nov 11, 2017 
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    Open source architectures or simulators that are focused on parallel processing.
GPGPU processor from team at University of Madison-Wisconsin.
- Status: low activity
- Instruction Set: AMD Southern Islands
- License: BSD
- Synthesizable: Yes
Manycore processor from team at Princeton. Core is based on OpenSPARC T1, but this replaces the crossbar switch and shared L2 cache of the former with a scalable 2D mesh network-on-chip.
- Status: active
- Instruction Set: SPARC
- License: GPLv2
- Synthesizable: Yes
Cycle-accurate compute core simulator based on NVidia architecture by team at University of British Columbia. Executes NVidia PTX intermediate code.
- Status: Last change was 2 years ago
- Instruction Set: NVidia PTX
- License: BSD
- Synthesizable: No
Synthesizable General-Purpose SIMT Processor. Supports hardware multithreading. Uses RISC-V (32I) instruction set.
- Status: Inactive (?)
- Instruction Set: RISC-V 32i (integer only)
- License: None
- Synthesizable: Yes
Simulator and Verilog compute core with a custom instruction set.
- Status: Inactive
- Instruction Set: Custom
- License: ?
- Synthesizable: Yes