[circt] LowerMemory might not update module hierarchy properly

[tianrui-wei]

When running the latest firtool with both --export-module-hierarchy and --repl-seq-mem flags, the sram names transformation might only happen in one place.

This manifests as in the smems.conf, there is only name rob_debug_inst_mem_ext ..., but in the model hierarchy json, the module only exists as rob_debug_inst_mem.

This can be verified as running the following commands in the chipyard repo at main branch after initializing the repo with https://chipyard.readthedocs.io/en/main/Chipyard-Basics/Initial-Repo-Setup.html.

make verilog USE_CHISEL7=1 CONFIG=MediumBoomV3Config

Note the curious thing is that this works for the first 17 sram transformation, just not for the last one. Let me know what I can help to diagnose this issue.

[tianrui-wei]

edit: the bug turned out to occur in conjunction with sifive.enterprise.firrtl.ModuleHierarchyAnnotation, will work with chisel folks to further diagnose the issue. Closing for now.

[tianrui-wei]

Reopening this issue after conversation with @jackkoenig. This seems to be a bug in the firtool. The issue can be reproduced by running run.sh in the attachment. The bug, mentioned above, manifests as the smem instance of ebtb gets transformed properly, but the rob_debug_inst_mem does not gets renamed properly in the module hierarchy json file.

repro.tar.gz