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[ARM] Remove most post-decoding instruction adjustments
1 parent f52e2bd commit 204f13a

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7 files changed

+231
-128
lines changed

7 files changed

+231
-128
lines changed

‎llvm/lib/Target/ARM/ARMInstrCDE.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@ class CDE_CX1_Instr<string iname, CX_Params params>
115115
!con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
116116
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
117117
params.Cstr> {
118+
bits<0> p;
118119
bits<13> imm;
119120
bits<4> Rd;
120121

@@ -131,6 +132,7 @@ class CDE_CX2_Instr<string iname, CX_Params params>
131132
!con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
132133
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
133134
params.Cstr> {
135+
bits<0> p;
134136
bits<9> imm;
135137
bits<4> Rd;
136138
bits<4> Rn;
@@ -149,6 +151,7 @@ class CDE_CX3_Instr<string iname, CX_Params params>
149151
!con(params.Iops3, (ins imm_6b:$imm), params.PredOp),
150152
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
151153
params.Cstr> {
154+
bits<0> p;
152155
bits<6> imm;
153156
bits<4> Rd;
154157
bits<4> Rn;
@@ -268,6 +271,7 @@ class CDE_Vec_Instr<bit acc, dag oops, dag iops, string asm, string cstr,
268271
!con(iops, (ins vpred:$vp)), asm,
269272
!strconcat(cstr, vpred.vpred_constraint)>,
270273
CDE_RequiresQReg {
274+
bits<0> vp;
271275
}
272276

273277

‎llvm/lib/Target/ARM/ARMInstrFormats.td‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1219,6 +1219,8 @@ class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
12191219
InstrItinClass itin,
12201220
string opc, string asm, string cstr, list<dag> pattern>
12211221
: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1222+
bits<0> s;
1223+
bits<0> p;
12221224
let OutOperandList = !con(oops, (outs s_cc_out:$s));
12231225
let InOperandList = !con(iops, (ins pred:$p));
12241226
let AsmString = !strconcat(opc, "${s}${p}", asm);
@@ -1243,6 +1245,7 @@ class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
12431245
InstrItinClass itin,
12441246
string opc, string asm, string cstr, list<dag> pattern>
12451247
: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1248+
bits<0> p;
12461249
let OutOperandList = oops;
12471250
let InOperandList = !con(iops, (ins pred:$p));
12481251
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1341,7 +1344,8 @@ class T1Misc<bits<7> opcode> : Encoding16 {
13411344
class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
13421345
InstrItinClass itin,
13431346
string opc, string asm, string cstr, list<dag> pattern>
1344-
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1347+
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1348+
bits<0> p;
13451349
let OutOperandList = oops;
13461350
let InOperandList = !con(iops, (ins pred:$p));
13471351
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1360,6 +1364,7 @@ class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
13601364
InstrItinClass itin,
13611365
string opc, string asm, string cstr, list<dag> pattern>
13621366
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1367+
bits<0> p;
13631368
bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
13641369
let Inst{20} = s;
13651370

@@ -2220,6 +2225,7 @@ class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
22202225
InstrItinClass itin, string opc, string dt, string asm, string cstr,
22212226
list<dag> pattern>
22222227
: InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
2228+
bits<0> p;
22232229
let OutOperandList = oops;
22242230
let InOperandList = !con(iops, (ins pred:$p));
22252231
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
@@ -2233,6 +2239,7 @@ class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
22332239
InstrItinClass itin, string opc, string asm, string cstr,
22342240
list<dag> pattern>
22352241
: InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
2242+
bits<0> p;
22362243
let OutOperandList = oops;
22372244
let InOperandList = !con(iops, (ins pred:$p));
22382245
let AsmString = !strconcat(opc, "${p}", "\t", asm);

‎llvm/lib/Target/ARM/ARMInstrMVE.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -409,6 +409,7 @@ class MVE_p<dag oops, dag iops, InstrItinClass itin, string iname,
409409
!strconcat(iname, "${vp}",
410410
!if(!eq(suffix, ""), "", !strconcat(".", suffix))),
411411
ops, !strconcat(cstr, vpred.vpred_constraint), vecsize, pattern> {
412+
bits<0> vp;
412413
let Inst{31-29} = 0b111;
413414
let Inst{27-26} = 0b11;
414415
}

‎llvm/lib/Target/ARM/ARMInstrThumb.td‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -483,6 +483,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
483483
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
484484
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
485485
// A6.2.3 & A8.6.25
486+
bits<0> p;
486487
bits<4> Rm;
487488
let Inst{6-3} = Rm;
488489
let Inst{2-0} = 0b000;
@@ -491,6 +492,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
491492
def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
492493
Requires<[IsThumb, Has8MSecExt]>,
493494
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
495+
bits<0> p;
494496
bits<4> Rm;
495497
let Inst{6-3} = Rm;
496498
let Inst{2-0} = 0b100;
@@ -523,6 +525,7 @@ let isCall = 1,
523525
"bl${p}\t$func",
524526
[(ARMcall tglobaladdr:$func)]>,
525527
Requires<[IsThumb]>, Sched<[WriteBrL]> {
528+
bits<0> p;
526529
bits<24> func;
527530
let Inst{26} = func{23};
528531
let Inst{25-16} = func{20-11};
@@ -536,6 +539,7 @@ let isCall = 1,
536539
(outs), (ins pred:$p, thumb_blx_target:$func), IIC_Br,
537540
"blx${p}\t$func", []>,
538541
Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
542+
bits<0> p;
539543
bits<24> func;
540544
let Inst{26} = func{23};
541545
let Inst{25-16} = func{20-11};
@@ -550,6 +554,7 @@ let isCall = 1,
550554
"blx${p}\t$func", []>,
551555
Requires<[IsThumb, HasV5T]>,
552556
T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
557+
bits<0> p;
553558
bits<4> func;
554559
let Inst{6-3} = func;
555560
let Inst{2-0} = 0b000;
@@ -565,6 +570,7 @@ let isCall = 1,
565570
"blxns${p}\t$func", []>,
566571
Requires<[IsThumb, Has8MSecExt]>,
567572
T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {
573+
bits<0> p;
568574
bits<4> func;
569575
let Inst{6-3} = func;
570576
let Inst{2-0} = 0b100;
@@ -824,6 +830,7 @@ let hasSideEffects = 0 in {
824830
let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
825831
def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
826832
IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
833+
bits<0> p;
827834
bits<3> Rn;
828835
bits<8> regs;
829836
let Inst{10-8} = Rn;
@@ -854,6 +861,7 @@ def tSTMIA_UPD : Thumb1I<(outs tGPR:$wb),
854861
AddrModeNone, 2, IIC_iStore_mu,
855862
"stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
856863
T1Encoding<{1,1,0,0,0,?}> {
864+
bits<0> p;
857865
bits<3> Rn;
858866
bits<8> regs;
859867
let Inst{10-8} = Rn;
@@ -872,6 +880,7 @@ def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
872880
IIC_iPop,
873881
"pop${p}\t$regs", []>,
874882
T1Misc<{1,1,0,?,?,?,?}>, Sched<[WriteLd]> {
883+
bits<0> p;
875884
bits<16> regs;
876885
let Inst{8} = regs{15};
877886
let Inst{7-0} = regs{7-0};
@@ -882,6 +891,7 @@ def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
882891
IIC_iStore_m,
883892
"push${p}\t$regs", []>,
884893
T1Misc<{0,1,0,?,?,?,?}>, Sched<[WriteST]> {
894+
bits<0> p;
885895
bits<16> regs;
886896
let Inst{8} = regs{14};
887897
let Inst{7-0} = regs{7-0};

‎llvm/lib/Target/ARM/ARMInstrThumb2.td‎

Lines changed: 20 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2059,6 +2059,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
20592059
def IA :
20602060
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
20612061
itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
2062+
bits<0> p;
20622063
bits<4> Rn;
20632064
bits<16> regs;
20642065

@@ -2074,6 +2075,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
20742075
def IA_UPD :
20752076
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
20762077
itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
2078+
bits<0> p;
20772079
bits<4> Rn;
20782080
bits<16> regs;
20792081

@@ -2089,6 +2091,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
20892091
def DB :
20902092
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
20912093
itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
2094+
bits<0> p;
20922095
bits<4> Rn;
20932096
bits<16> regs;
20942097

@@ -2104,6 +2107,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
21042107
def DB_UPD :
21052108
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21062109
itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2110+
bits<0> p;
21072111
bits<4> Rn;
21082112
bits<16> regs;
21092113

@@ -2128,6 +2132,7 @@ multiclass thumb2_st_mult<string asm, InstrItinClass itin,
21282132
def IA :
21292133
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21302134
itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
2135+
bits<0> p;
21312136
bits<4> Rn;
21322137
bits<16> regs;
21332138

@@ -2146,6 +2151,7 @@ multiclass thumb2_st_mult<string asm, InstrItinClass itin,
21462151
def IA_UPD :
21472152
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21482153
itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
2154+
bits<0> p;
21492155
bits<4> Rn;
21502156
bits<16> regs;
21512157

@@ -2164,6 +2170,7 @@ multiclass thumb2_st_mult<string asm, InstrItinClass itin,
21642170
def DB :
21652171
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21662172
itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
2173+
bits<0> p;
21672174
bits<4> Rn;
21682175
bits<16> regs;
21692176

@@ -2182,6 +2189,7 @@ multiclass thumb2_st_mult<string asm, InstrItinClass itin,
21822189
def DB_UPD :
21832190
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21842191
itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2192+
bits<0> p;
21852193
bits<4> Rn;
21862194
bits<16> regs;
21872195

@@ -4030,9 +4038,11 @@ def t2TBH : T2I<(outs), (ins (addrmode_tbh $Rn, $Rm):$addr), IIC_Br,
40304038
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
40314039
// a two-value operand where a dag node expects ", "two operands. :(
40324040
let isBranch = 1, isTerminator = 1 in
4033-
def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
4034-
"b", ".w\t$target",
4035-
[/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
4041+
def t2Bcc : Thumb2XI<(outs), (ins brtarget:$target, pred:$p),
4042+
AddrModeNone, 4, IIC_Br,
4043+
"b${p}.w\t$target", "",
4044+
[/*(ARMbrcond bb:$target, imm:$cc)*/]>,
4045+
Sched<[WriteBr]> {
40364046
let Inst{31-27} = 0b11110;
40374047
let Inst{15-14} = 0b10;
40384048
let Inst{12} = 0;
@@ -5488,6 +5498,7 @@ class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm,
54885498
def t2CLRM : V8_1MI<(outs),
54895499
(ins pred:$p, reglist_with_apsr:$regs, variable_ops),
54905500
AddrModeNone, NoItinerary, "clrm${p}", "$regs", "", []> {
5501+
bits<0> p;
54915502
bits<16> regs;
54925503

54935504
let Inst{31-16} = 0b1110100010011111;
@@ -5516,6 +5527,7 @@ def t2BF_LabelPseudo
55165527

55175528
def t2BFi : t2BF<(ins bflabel_u4:$b_label, bflabel_s16:$label, pred:$p),
55185529
!strconcat("bf", "${p}"), "$b_label, $label"> {
5530+
bits<0> p;
55195531
bits<4> b_label;
55205532
bits<16> label;
55215533

@@ -5547,6 +5559,7 @@ def t2BFic : t2BF<(ins bflabel_u4:$b_label, bflabel_s12:$label,
55475559

55485560
def t2BFr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
55495561
!strconcat("bfx", "${p}"), "$b_label, $Rn"> {
5562+
bits<0> p;
55505563
bits<4> b_label;
55515564
bits<4> Rn;
55525565

@@ -5558,6 +5571,7 @@ def t2BFr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
55585571

55595572
def t2BFLi : t2BF<(ins bflabel_u4:$b_label, bflabel_s18:$label, pred:$p),
55605573
!strconcat("bfl", "${p}"), "$b_label, $label"> {
5574+
bits<0> p;
55615575
bits<4> b_label;
55625576
bits<18> label;
55635577

@@ -5570,6 +5584,7 @@ def t2BFLi : t2BF<(ins bflabel_u4:$b_label, bflabel_s18:$label, pred:$p),
55705584

55715585
def t2BFLr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
55725586
!strconcat("bflx", "${p}"), "$b_label, $Rn"> {
5587+
bits<0> p;
55735588
bits<4> b_label;
55745589
bits<4> Rn;
55755590

@@ -5810,6 +5825,7 @@ let Predicates = [IsThumb2, HasV8_1MMainline, HasPACBTI] in {
58105825
def t2PACG : V8_1MI<(outs rGPR:$Rd),
58115826
(ins pred:$p, GPRnopc:$Rn, GPRnopc:$Rm),
58125827
AddrModeNone, NoItinerary, "pacg${p}", "$Rd, $Rn, $Rm", "", []> {
5828+
bits<0> p;
58135829
bits<4> Rd;
58145830
bits<4> Rn;
58155831
bits<4> Rm;
@@ -5825,6 +5841,7 @@ let hasSideEffects = 1 in {
58255841
class PACBTIAut<dag iops, string asm, bit b>
58265842
: V8_1MI<(outs), iops,
58275843
AddrModeNone, NoItinerary, asm, "$Ra, $Rn, $Rm", "", []> {
5844+
bits<0> p;
58285845
bits<4> Ra;
58295846
bits<4> Rn;
58305847
bits<4> Rm;

‎llvm/lib/Target/ARM/CMakeLists.txt‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,7 @@ tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
66
tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
88
tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
9-
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler
10-
-ignore-non-decodable-operands)
9+
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
1110
tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
1211
tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
1312
tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)

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