From e65436c5dd3b89466680fb7065707b940ca916f0 Mon Sep 17 00:00:00 2001 From: John Lu Date: Tue, 7 Oct 2025 13:49:48 -0500 Subject: [PATCH 1/4] Pre-commit test for redundant s_cmp sX, 0 removal Signed-off-by: John Lu --- llvm/test/CodeGen/AMDGPU/s_cmp_0.ll | 585 ++++++++++++++++++++++++++++ 1 file changed, 585 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/s_cmp_0.ll diff --git a/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll b/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll new file mode 100644 index 0000000000000..8dc846c862200 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll @@ -0,0 +1,585 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s + +declare i32 @llvm.ctpop.i32(i32) +declare i64 @llvm.ctpop.i64(i64) +declare i32 @llvm.amdgcn.s.quadmask.i32(i32) +declare i64 @llvm.amdgcn.s.quadmask.i64(i64) + +define amdgpu_ps i32 @shl32(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: shl32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_lshl_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = shl i32 %val0, %val1 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @shl64(i64 inreg %val0, i64 inreg %val1) { +; CHECK-LABEL: shl64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = shl i64 %val0, %val1 + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @lshr32(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: lshr32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_lshr_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = lshr i32 %val0, %val1 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @lshr64(i64 inreg %val0, i64 inreg %val1) { +; CHECK-LABEL: lshr64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = lshr i64 %val0, %val1 + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @and32(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: and32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_and_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = and i32 %val0, %val1 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @and64(i64 inreg %val0, i64 inreg %val1) { +; CHECK-LABEL: and64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = and i64 %val0, %val1 + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @or32(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: or32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_or_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = or i32 %val0, %val1 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @or64(i64 inreg %val0, i64 inreg %val1) { +; CHECK-LABEL: or64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = or i64 %val0, %val1 + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @xor32(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: xor32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_xor_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = xor i32 %val0, %val1 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @xor64(i64 inreg %val0, i64 inreg %val1) { +; CHECK-LABEL: xor64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = xor i64 %val0, %val1 + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @nand32(i32 inreg %val0, i32 inreg %val1, ptr addrspace(1) %ptr) { +; CHECK-LABEL: nand32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_nand_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dword v[0:1], v2, off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = and i32 %val0, %val1 + %result2 = xor i32 %result, -1 + store i32 %result2, ptr addrspace(1) %ptr + %cmp = icmp ne i32 %result2, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @nand64(i64 inreg %val0, i64 inreg %val1, ptr addrspace(1) %ptr) { +; CHECK-LABEL: nand64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_nand_b64 s[0:1], s[0:1], s[2:3] +; CHECK-NEXT: v_mov_b32_e32 v3, s1 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = and i64 %val0, %val1 + %result2 = xor i64 %result, -1 + store i64 %result2, ptr addrspace(1) %ptr + %cmp = icmp ne i64 %result2, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @nor32(i32 inreg %val0, i32 inreg %val1, ptr addrspace(1) %ptr) { +; CHECK-LABEL: nor32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_nor_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dword v[0:1], v2, off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = or i32 %val0, %val1 + %result2 = xor i32 %result, -1 + store i32 %result2, ptr addrspace(1) %ptr + %cmp = icmp ne i32 %result2, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @nor64(i64 inreg %val0, i64 inreg %val1, ptr addrspace(1) %ptr) { +; CHECK-LABEL: nor64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_nor_b64 s[0:1], s[0:1], s[2:3] +; CHECK-NEXT: v_mov_b32_e32 v3, s1 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = or i64 %val0, %val1 + %result2 = xor i64 %result, -1 + store i64 %result2, ptr addrspace(1) %ptr + %cmp = icmp ne i64 %result2, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @xnor32(i32 inreg %val0, i32 inreg %val1, ptr addrspace(1) %ptr) { +; CHECK-LABEL: xnor32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_xnor_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dword v[0:1], v2, off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = xor i32 %val0, %val1 + %result2 = xor i32 %result, -1 + store i32 %result2, ptr addrspace(1) %ptr + %cmp = icmp ne i32 %result2, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @xnor64(i64 inreg %val0, i64 inreg %val1, ptr addrspace(1) %ptr) { +; CHECK-LABEL: xnor64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_xnor_b64 s[0:1], s[0:1], s[2:3] +; CHECK-NEXT: v_mov_b32_e32 v3, s1 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = xor i64 %val0, %val1 + %result2 = xor i64 %result, -1 + store i64 %result2, ptr addrspace(1) %ptr + %cmp = icmp ne i64 %result2, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @andn232(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: andn232: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_andn2_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %nval1 = xor i32 %val1, -1 + %result = and i32 %val0, %nval1 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @nandn264(i64 inreg %val0, i64 inreg %val1) { +; CHECK-LABEL: nandn264: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3] +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %nval1 = xor i64 %val1, -1 + %result = and i64 %val0, %nval1 + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @orn232(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: orn232: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_orn2_b32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %nval1 = xor i32 %val1, -1 + %result = or i32 %val0, %nval1 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @orn264(i64 inreg %val0, i64 inreg %val1) { +; CHECK-LABEL: orn264: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_orn2_b64 s[0:1], s[0:1], s[2:3] +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %nval1 = xor i64 %val1, -1 + %result = or i64 %val0, %nval1 + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @bfe_i32(i32 inreg %val0) { +; CHECK-LABEL: bfe_i32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_bfe_i32 s0, s0, 0x80010 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %shl = shl i32 %val0, 8 + %result = ashr i32 %shl, 24 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @bfe_i64(i64 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: bfe_i64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_bfe_i64 s[2:3], s[0:1], 0x80000 +; CHECK-NEXT: s_and_b32 s0, s0, 0xff +; CHECK-NEXT: s_mov_b32 s1, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s2 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: v_mov_b32_e32 v3, s3 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %shl = shl i64 %val0, 56 + %result = ashr i64 %shl, 56 + store i64 %result, ptr addrspace(1) %ptr + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @bfe_u32(i32 inreg %val0) { +; CHECK-LABEL: bfe_u32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_bfe_u32 s0, s0, 0x80010 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %shl = shl i32 %val0, 8 + %result = lshr i32 %shl, 24 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @bfe_u64(i64 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: bfe_u64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_and_b32 s0, s0, 0xff +; CHECK-NEXT: s_mov_b32 s1, 0 +; CHECK-NEXT: v_mov_b32_e32 v3, s1 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %shl = shl i64 %val0, 56 + %result = lshr i64 %shl, 56 + store i64 %result, ptr addrspace(1) %ptr + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @bcnt032(i32 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: bcnt032: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_bcnt1_i32_b32 s0, s0 +; CHECK-NEXT: s_sub_i32 s0, 32, s0 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dword v[0:1], v2, off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone + %result2 = sub i32 32, %result + store i32 %result2, ptr addrspace(1) %ptr + %cmp = icmp ne i32 %result2, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @bcnt064(i64 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: bcnt064: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_bcnt1_i32_b64 s0, s[0:1] +; CHECK-NEXT: s_sub_u32 s0, 64, s0 +; CHECK-NEXT: s_subb_u32 s1, 0, 0 +; CHECK-NEXT: v_mov_b32_e32 v3, s1 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = call i64 @llvm.ctpop.i64(i64 %val0) nounwind readnone + %result2 = sub i64 64, %result + store i64 %result2, ptr addrspace(1) %ptr + %cmp = icmp ne i64 %result2, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @bcnt132(i32 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: bcnt132: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_bcnt1_i32_b32 s0, s0 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dword v[0:1], v2, off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone + store i32 %result, ptr addrspace(1) %ptr + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @bcnt164(i64 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: bcnt164: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_bcnt1_i32_b64 s0, s[0:1] +; CHECK-NEXT: s_mov_b32 s1, 0 +; CHECK-NEXT: v_mov_b32_e32 v3, s1 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = call i64 @llvm.ctpop.i64(i64 %val0) nounwind readnone + store i64 %result, ptr addrspace(1) %ptr + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @quadmask32(i32 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: quadmask32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_quadmask_b32 s0, s0 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dword v[0:1], v2, off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = call i32 @llvm.amdgcn.s.quadmask.i32(i32 %val0) nounwind readnone + store i32 %result, ptr addrspace(1) %ptr + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @quadmask64(i64 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: quadmask64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_quadmask_b64 s[0:1], s[0:1] +; CHECK-NEXT: v_mov_b32_e32 v3, s1 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = call i64 @llvm.amdgcn.s.quadmask.i64(i64 %val0) nounwind readnone + store i64 %result, ptr addrspace(1) %ptr + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @not32(i32 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: not32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_not_b32 s0, s0 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dword v[0:1], v2, off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = xor i32 %val0, -1 + store i32 %result, ptr addrspace(1) %ptr + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @not64(i64 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: not64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_not_b64 s[0:1], s[0:1] +; CHECK-NEXT: v_mov_b32_e32 v3, s1 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %result = xor i64 %val0, -1 + store i64 %result, ptr addrspace(1) %ptr + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + + From 050ff9636ecd268ecdb475adc9c18a23c747a163 Mon Sep 17 00:00:00 2001 From: John Lu Date: Tue, 7 Oct 2025 23:20:34 -0500 Subject: [PATCH 2/4] Remove empty lines at end of file Signed-off-by: John Lu --- llvm/test/CodeGen/AMDGPU/s_cmp_0.ll | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll b/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll index 8dc846c862200..608e792236316 100644 --- a/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll +++ b/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll @@ -581,5 +581,3 @@ define amdgpu_ps i32 @not64(i64 inreg %val0, ptr addrspace(1) %ptr) { %zext = zext i1 %cmp to i32 ret i32 %zext } - - From dca3d5a89c1815a23d980d20e01ac59e5c9a74de Mon Sep 17 00:00:00 2001 From: John Lu Date: Wed, 8 Oct 2025 22:50:23 -0500 Subject: [PATCH 3/4] Test more instructions Signed-off-by: John Lu --- llvm/test/CodeGen/AMDGPU/s_cmp_0.ll | 51 +++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll b/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll index 608e792236316..3e002eee551de 100644 --- a/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll +++ b/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll @@ -66,6 +66,57 @@ define amdgpu_ps i32 @lshr64(i64 inreg %val0, i64 inreg %val1) { ret i32 %zext } +define amdgpu_ps i32 @ashr32(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: ashr32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_ashr_i32 s0, s0, s1 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = ashr i32 %val0, %val1 + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @ashr64(i64 inreg %val0, i64 inreg %val1) { +; CHECK-LABEL: ashr64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_ashr_i64 s[0:1], s[0:1], s2 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %result = ashr i64 %val0, %val1 + %cmp = icmp ne i64 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + +define amdgpu_ps i32 @abs32(i32 inreg %val0, ptr addrspace(1) %ptr) { +; CHECK-LABEL: abs32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_abs_i32 s0, s0 +; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 +; CHECK-NEXT: global_store_dword v[0:1], v2, off +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ; return to shader part epilog + %neg = sub i32 0, %val0 + %cond = icmp sgt i32 %val0, %neg + %result = select i1 %cond, i32 %val0, i32 %neg + store i32 %result, ptr addrspace(1) %ptr + %cmp = icmp ne i32 %result, 0 + %zext = zext i1 %cmp to i32 + ret i32 %zext +} + define amdgpu_ps i32 @and32(i32 inreg %val0, i32 inreg %val1) { ; CHECK-LABEL: and32: ; CHECK: ; %bb.0: From cf1ecd1f887e9e9a230a5acec0d3cc666776d3c7 Mon Sep 17 00:00:00 2001 From: John Lu Date: Fri, 10 Oct 2025 08:53:03 -0500 Subject: [PATCH 4/4] Simplify extra use Signed-off-by: John Lu --- llvm/test/CodeGen/AMDGPU/s_cmp_0.ll | 179 +++++++++++++--------------- 1 file changed, 85 insertions(+), 94 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll b/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll index 3e002eee551de..f53aaaad87e16 100644 --- a/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll +++ b/llvm/test/CodeGen/AMDGPU/s_cmp_0.ll @@ -96,22 +96,22 @@ define amdgpu_ps i32 @ashr64(i64 inreg %val0, i64 inreg %val1) { ret i32 %zext } -define amdgpu_ps i32 @abs32(i32 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @abs32(i32 inreg %val0) { ; CHECK-LABEL: abs32: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_abs_i32 s0, s0 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s0 +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %neg = sub i32 0, %val0 %cond = icmp sgt i32 %val0, %neg %result = select i1 %cond, i32 %val0, i32 %neg - store i32 %result, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i32 %result) %cmp = icmp ne i32 %result, 0 %zext = zext i1 %cmp to i32 ret i32 %zext @@ -207,124 +207,121 @@ define amdgpu_ps i32 @xor64(i64 inreg %val0, i64 inreg %val1) { ret i32 %zext } -define amdgpu_ps i32 @nand32(i32 inreg %val0, i32 inreg %val1, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @nand32(i32 inreg %val0, i32 inreg %val1) { ; CHECK-LABEL: nand32: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_nand_b32 s0, s0, s1 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s0 +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = and i32 %val0, %val1 %result2 = xor i32 %result, -1 - store i32 %result2, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i32 %result2) %cmp = icmp ne i32 %result2, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @nand64(i64 inreg %val0, i64 inreg %val1, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @nand64(i64 inreg %val0, i64 inreg %val1) { ; CHECK-LABEL: nand64: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_nand_b64 s[0:1], s[0:1], s[2:3] -; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s[0:1] +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = and i64 %val0, %val1 %result2 = xor i64 %result, -1 - store i64 %result2, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i64 %result2) %cmp = icmp ne i64 %result2, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @nor32(i32 inreg %val0, i32 inreg %val1, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @nor32(i32 inreg %val0, i32 inreg %val1) { ; CHECK-LABEL: nor32: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_nor_b32 s0, s0, s1 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s0 +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = or i32 %val0, %val1 %result2 = xor i32 %result, -1 - store i32 %result2, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i32 %result2) %cmp = icmp ne i32 %result2, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @nor64(i64 inreg %val0, i64 inreg %val1, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @nor64(i64 inreg %val0, i64 inreg %val1) { ; CHECK-LABEL: nor64: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_nor_b64 s[0:1], s[0:1], s[2:3] -; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s[0:1] +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = or i64 %val0, %val1 %result2 = xor i64 %result, -1 - store i64 %result2, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i64 %result2) %cmp = icmp ne i64 %result2, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @xnor32(i32 inreg %val0, i32 inreg %val1, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @xnor32(i32 inreg %val0, i32 inreg %val1) { ; CHECK-LABEL: xnor32: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_xnor_b32 s0, s0, s1 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s0 +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = xor i32 %val0, %val1 %result2 = xor i32 %result, -1 - store i32 %result2, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i32 %result2) %cmp = icmp ne i32 %result2, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @xnor64(i64 inreg %val0, i64 inreg %val1, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @xnor64(i64 inreg %val0, i64 inreg %val1) { ; CHECK-LABEL: xnor64: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_xnor_b64 s[0:1], s[0:1], s[2:3] -; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s[0:1] +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = xor i64 %val0, %val1 %result2 = xor i64 %result, -1 - store i64 %result2, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i64 %result2) %cmp = icmp ne i64 %result2, 0 %zext = zext i1 %cmp to i32 ret i32 %zext @@ -410,24 +407,23 @@ define amdgpu_ps i32 @bfe_i32(i32 inreg %val0) { ret i32 %zext } -define amdgpu_ps i32 @bfe_i64(i64 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @bfe_i64(i64 inreg %val0) { ; CHECK-LABEL: bfe_i64: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_bfe_i64 s[2:3], s[0:1], 0x80000 ; CHECK-NEXT: s_and_b32 s0, s0, 0xff ; CHECK-NEXT: s_mov_b32 s1, 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s2 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 -; CHECK-NEXT: v_mov_b32_e32 v3, s3 ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s[2:3] +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ; return to shader part epilog %shl = shl i64 %val0, 56 %result = ashr i64 %shl, 56 - store i64 %result, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i64 %result) %cmp = icmp ne i64 %result, 0 %zext = zext i1 %cmp to i32 ret i32 %zext @@ -449,185 +445,180 @@ define amdgpu_ps i32 @bfe_u32(i32 inreg %val0) { ret i32 %zext } -define amdgpu_ps i32 @bfe_u64(i64 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @bfe_u64(i64 inreg %val0) { ; CHECK-LABEL: bfe_u64: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_and_b32 s0, s0, 0xff ; CHECK-NEXT: s_mov_b32 s1, 0 -; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s[0:1] +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %shl = shl i64 %val0, 56 %result = lshr i64 %shl, 56 - store i64 %result, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i64 %result) %cmp = icmp ne i64 %result, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @bcnt032(i32 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @bcnt032(i32 inreg %val0) { ; CHECK-LABEL: bcnt032: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_bcnt1_i32_b32 s0, s0 ; CHECK-NEXT: s_sub_i32 s0, 32, s0 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s0 +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone %result2 = sub i32 32, %result - store i32 %result2, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i32 %result2) %cmp = icmp ne i32 %result2, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @bcnt064(i64 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @bcnt064(i64 inreg %val0) { ; CHECK-LABEL: bcnt064: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_bcnt1_i32_b64 s0, s[0:1] ; CHECK-NEXT: s_sub_u32 s0, 64, s0 ; CHECK-NEXT: s_subb_u32 s1, 0, 0 -; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s[0:1] +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = call i64 @llvm.ctpop.i64(i64 %val0) nounwind readnone %result2 = sub i64 64, %result - store i64 %result2, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i64 %result2) %cmp = icmp ne i64 %result2, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @bcnt132(i32 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @bcnt132(i32 inreg %val0) { ; CHECK-LABEL: bcnt132: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_bcnt1_i32_b32 s0, s0 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s0 +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone - store i32 %result, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i32 %result) %cmp = icmp ne i32 %result, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @bcnt164(i64 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @bcnt164(i64 inreg %val0) { ; CHECK-LABEL: bcnt164: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_bcnt1_i32_b64 s0, s[0:1] ; CHECK-NEXT: s_mov_b32 s1, 0 -; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s[0:1] +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = call i64 @llvm.ctpop.i64(i64 %val0) nounwind readnone - store i64 %result, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i64 %result) %cmp = icmp ne i64 %result, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @quadmask32(i32 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @quadmask32(i32 inreg %val0) { ; CHECK-LABEL: quadmask32: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_quadmask_b32 s0, s0 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s0 +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = call i32 @llvm.amdgcn.s.quadmask.i32(i32 %val0) nounwind readnone - store i32 %result, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i32 %result) %cmp = icmp ne i32 %result, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @quadmask64(i64 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @quadmask64(i64 inreg %val0) { ; CHECK-LABEL: quadmask64: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_quadmask_b64 s[0:1], s[0:1] -; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s[0:1] +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = call i64 @llvm.amdgcn.s.quadmask.i64(i64 %val0) nounwind readnone - store i64 %result, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i64 %result) %cmp = icmp ne i64 %result, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @not32(i32 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @not32(i32 inreg %val0) { ; CHECK-LABEL: not32: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_not_b32 s0, s0 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s0 +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = xor i32 %val0, -1 - store i32 %result, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i32 %result) %cmp = icmp ne i32 %result, 0 %zext = zext i1 %cmp to i32 ret i32 %zext } -define amdgpu_ps i32 @not64(i64 inreg %val0, ptr addrspace(1) %ptr) { +define amdgpu_ps i32 @not64(i64 inreg %val0) { ; CHECK-LABEL: not64: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_not_b64 s[0:1], s[0:1] -; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 -; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; use s[0:1] +; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 -; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 -; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; return to shader part epilog %result = xor i64 %val0, -1 - store i64 %result, ptr addrspace(1) %ptr + call void asm "; use $0", "s"(i64 %result) %cmp = icmp ne i64 %result, 0 %zext = zext i1 %cmp to i32 ret i32 %zext