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lromorlromor
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xilinx: added xilinx 7 series architecture definitions and configuration packet
1 parent 2f49a1c commit 2a32286

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+1915
-20
lines changed

‎.github/workflows/ci.yml‎

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@@ -62,12 +62,12 @@ jobs:
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- name: Install Dependencies
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run: |
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sudo apt-get install clang-format-18
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sudo apt-get install clang-format-17
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- name: Run formatting style check
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run: |
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clang-format-18 --version
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RUNNING_IN_CI=1 CLANG_FORMAT=clang-format-18 \
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clang-format-17 --version
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RUNNING_IN_CI=1 CLANG_FORMAT=clang-format-17 \
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scripts/run-clang-format.sh
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ClangTidy:

‎MODULE.bazel‎

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@@ -16,16 +16,7 @@ git_override(
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bazel_dep(name = "abseil-cpp", version = "20240722.0.bcr.2")
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bazel_dep(name = "googletest", version = "1.15.2")
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bazel_dep(name = "rapidjson", version = "1.1.0.bcr.20241007")
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## C/C++ deps from local registry.
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bazel_dep(name = "prjxray", version = "0.0-583-t1e53270")
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git_override(
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module_name = "prjxray",
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commit = "3a95169e555de315c6b4cb71249107972d944303",
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patch_strip = 1,
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patches = ["//bazel:prjxray-add-module-bazel.patch"],
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remote = "https://github.com/f4pga/prjxray.git",
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)
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bazel_dep(name = "rules_license", version = "1.0.0")
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# compilation DB; build_cleaner
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bazel_dep(name = "bant", version = "0.1.14", dev_dependency = True)

‎README.md‎

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@@ -30,10 +30,6 @@ or install in system directory that requires root-access:
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sudo install -D --strip bazel-bin/fpga/fpga-as /usr/local/bin/fpga-as
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```
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[fasm-spec]: https://fasm.readthedocs.io/en/stable/#
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[bazel]: https://bazel.build/
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[counter-example]: https://github.com/chipsalliance/f4pga-examples/blob/13f11197b33dae1cde3bf146f317d63f0134eacf/xc7/counter_test/counter.v
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# How it works
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## Frames generation
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* offset: `77`
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Using this metadata, you can search the segbits database for the specific feature. By matching the tile_type and the FASM feature name, you can identify the correct configuration bits in the tile type segbits file (`segbits_clblm_r.db`). In this case, you would look for the entry corresponding to CLBLM_R.SLICEM_X0.ALUT.INIT and find the entry for address `[34]`. The value 34_06 then provides the coordinates for the word index and the specific bit index to be set.
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[fasm-spec]: https://fasm.readthedocs.io/en/stable/#
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[bazel]: https://bazel.build/
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[counter-example]: https://github.com/chipsalliance/f4pga-examples/blob/13f11197b33dae1cde3bf146f317d63f0134eacf/xc7/counter_test/counter.v

‎fpga/assembler.cc‎

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@@ -430,7 +430,7 @@ int main(int argc, char *argv[]) {
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<< '\n';
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return EXIT_FAILURE;
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}
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PrintFrames(frames, std::cout, false);
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// Write bitstream
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return EXIT_SUCCESS;
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}

‎fpga/database-parsers_test.cc‎

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#include "gtest/gtest.h"
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namespace fpga {
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template <typename Sink>
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void AbslStringify(Sink &sink, const TileFeature &e) {
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absl::Format(&sink, "(tile_feature=\"%s\", address=%d)", e.tile_feature,

‎fpga/xilinx/BUILD‎

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load("@rules_cc//cc:defs.bzl", "cc_library", "cc_test")
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load("@rules_license//rules:license.bzl", "license")
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package(
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default_applicable_licenses = [":license"],
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default_visibility = ["//:__subpackages__"],
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)
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license(
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name = "license",
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package_name = "xilinx",
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license_kind = "@rules_license//licenses/spdx:ISC",
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)
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cc_library(
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name = "big-endian-span",
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hdrs = [
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"big-endian-span.h",
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],
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deps = [
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"@abseil-cpp//absl/types:span",
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],
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)
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cc_test(
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name = "big-endian-span_test",
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srcs = [
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"big-endian-span_test.cc",
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],
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deps = [
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":big-endian-span",
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"@googletest//:gtest",
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"@googletest//:gtest_main",
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],
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)
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cc_library(
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name = "bit-ops",
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hdrs = [
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"bit-ops.h",
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],
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)
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cc_test(
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name = "bit-ops_test",
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srcs = [
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"bit-ops_test.cc",
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],
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deps = [
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":bit-ops",
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"@googletest//:gtest",
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"@googletest//:gtest_main",
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],
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)
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cc_library(
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name = "configuration-packet",
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hdrs = [
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"configuration-packet.h",
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],
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deps = [
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"@abseil-cpp//absl/types:optional",
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"@abseil-cpp//absl/types:span",
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],
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)
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cc_library(
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name = "arch-xc7-defs",
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srcs = [
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"arch-xc7-defs.cc",
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],
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hdrs = [
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"arch-xc7-defs.h",
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],
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)
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cc_library(
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name = "arch-xc7-configuration-packet",
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srcs = [
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"arch-xc7-configuration-packet.cc",
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],
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hdrs = [
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"arch-xc7-configuration-packet.h",
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],
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deps = [
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":arch-xc7-defs",
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":bit-ops",
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":configuration-packet",
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"@abseil-cpp//absl/types:span",
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],
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)
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cc_test(
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name = "arch-xc7-configuration-packet_test",
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srcs = [
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"arch-xc7-configuration-packet_test.cc",
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],
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deps = [
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":arch-xc7-configuration-packet",
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":arch-xc7-defs",
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":bit-ops",
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"@abseil-cpp//absl/types:span",
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"@googletest//:gtest",
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"@googletest//:gtest_main",
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],
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)
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cc_library(
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name = "arch-xc7-frame-address",
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srcs = [
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"arch-xc7-frame-address.cc",
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],
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hdrs = [
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"arch-xc7-frame-address.h",
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],
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deps = [
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":arch-xc7-defs",
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":bit-ops",
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],
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)
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cc_library(
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name = "arch-xc7-part",
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srcs = [
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"arch-xc7-part.cc",
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],
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hdrs = [
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"arch-xc7-part.h",
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],
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deps = [
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":arch-xc7-defs",
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":arch-xc7-frame-address",
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],
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)
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cc_test(
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name = "arch-xc7-part_test",
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srcs = [
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"arch-xc7-part_test.cc",
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],
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deps = [
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":arch-xc7-defs",
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":arch-xc7-frame-address",
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":arch-xc7-part",
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"@googletest//:gtest",
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"@googletest//:gtest_main",
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],
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)

‎fpga/xilinx/README.md‎

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# Xilinx Bitstream Generation
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Most of this code originates from [prjxray][prjxray]. It was imported into this repository to simplify type interfacing and eliminate the dependency on yaml-cpp, which requires exceptions to be enabled.
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[prjxray]: https://github.com/f4pga/prjxray/tree/faf9c774a340e39cf6802d009996ed6016e63521/lib

‎fpga/xilinx/arch-xc7-configuration-packet.cc‎

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#include "fpga/xilinx/arch-xc7-configuration-packet.h"
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#include <cstdint>
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#include <optional>
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#include "absl/types/span.h"
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#include "fpga/xilinx/arch-xc7-defs.h"
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#include "fpga/xilinx/bit-ops.h"
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#include "fpga/xilinx/configuration-packet.h"
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namespace fpga {
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namespace xilinx {
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namespace xc7 {
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ConfigurationPacket::ParseResult ConfigurationPacket::InitWithWordsImpl(
15+
absl::Span<uint32_t> words, const ConfigurationPacket *previous_packet) {
16+
using ConfigurationRegister = ConfigurationRegister;
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// Need at least one 32-bit word to have a valid packet header.
18+
if (words.empty()) {
19+
return {words, {}};
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}
21+
const ConfigurationPacketType header_type =
22+
static_cast<ConfigurationPacketType>(bit_field_get(words[0], 31, 29));
23+
switch (header_type) {
24+
case ConfigurationPacketType::kNONE:
25+
// Type 0 is emitted at the end of a configuration row
26+
// when BITSTREAM.GENERAL.DEBUGBITSTREAM is set to YES.
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// These seem to be padding that are interepreted as
28+
// NOPs. Since Type 0 packets don't exist according to
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// UG470 and they seem to be zero-filled, just consume
30+
// the bytes without generating a packet.
31+
return {words.subspan(1),
32+
{{static_cast<uint32_t>(header_type),
33+
Opcode::kNOP,
34+
ConfigurationRegister::kCRC,
35+
{}}}};
36+
case ConfigurationPacketType::kTYPE1: {
37+
const Opcode opcode = static_cast<Opcode>(bit_field_get(words[0], 28, 27));
38+
const ConfigurationRegister address =
39+
static_cast<ConfigurationRegister>(bit_field_get(words[0], 26, 13));
40+
const uint32_t data_word_count = bit_field_get(words[0], 10, 0);
41+
42+
// If the full packet has not been received, return as
43+
// though no valid packet was found.
44+
if (data_word_count > words.size() - 1) {
45+
return {words, {}};
46+
}
47+
48+
return {words.subspan(data_word_count + 1),
49+
{{static_cast<uint32_t>(header_type), opcode, address,
50+
words.subspan(1, data_word_count)}}};
51+
}
52+
case ConfigurationPacketType::kTYPE2: {
53+
std::optional<ConfigurationPacket> packet;
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const Opcode opcode = static_cast<Opcode>(bit_field_get(words[0], 28, 27));
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const uint32_t data_word_count = bit_field_get(words[0], 26, 0);
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// If the full packet has not been received, return as
58+
// though no valid packet was found.
59+
if (data_word_count > words.size() - 1) {
60+
return {words, {}};
61+
}
62+
63+
if (previous_packet) {
64+
packet = ConfigurationPacket(static_cast<uint32_t>(header_type), opcode,
65+
previous_packet->address(),
66+
words.subspan(1, data_word_count));
67+
}
68+
69+
return {words.subspan(data_word_count + 1), packet};
70+
}
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default: return {{}, {}};
72+
}
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}
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} // namespace xc7
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} // namespace xilinx
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} // namespace fpga

‎fpga/xilinx/arch-xc7-configuration-packet.h‎

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/*
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* Copyright (C) 2017-2020 The Project X-Ray Authors.
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*
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* Use of this source code is governed by a ISC-style
5+
* license that can be found in the LICENSE file or at
6+
* https://opensource.org/licenses/ISC
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*
8+
* SPDX-License-Identifier: ISC
9+
*/
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#ifndef FPGA_XILINX_ARCH_XC7_CONFIGURATION_PACKET_H
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#define FPGA_XILINX_ARCH_XC7_CONFIGURATION_PACKET_H
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13+
#include <cstdint>
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#include <memory>
15+
#include <vector>
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#include "absl/types/span.h"
18+
#include "fpga/xilinx/arch-xc7-defs.h"
19+
#include "fpga/xilinx/configuration-packet.h"
20+
21+
namespace fpga {
22+
namespace xilinx {
23+
namespace xc7 {
24+
class ConfigurationPacket
25+
: public ConfigurationPacketBase<ConfigurationRegister,
26+
ConfigurationPacket> {
27+
private:
28+
using BaseType =
29+
ConfigurationPacketBase<ConfigurationRegister, ConfigurationPacket>;
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public:
32+
using BaseType::BaseType;
33+
34+
private:
35+
friend BaseType;
36+
static ParseResult InitWithWordsImpl(
37+
absl::Span<uint32_t> words,
38+
const ConfigurationPacket *previous_packet = nullptr);
39+
};
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using ConfigurationPackage = std::vector<std::unique_ptr<ConfigurationPacket>>;
42+
} // namespace xc7
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} // namespace xilinx
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} // namespace fpga
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#endif // FPGA_XILINX_ARCH_XC7_CONFIGURATION_PACKET_H

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