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lromorlromor
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xilinx: added xilinx 7 series architecture definitions and configuration packet
1 parent 2f49a1c commit 88f60fd

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+736
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‎MODULE.bazel‎

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@@ -16,16 +16,7 @@ git_override(
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bazel_dep(name = "abseil-cpp", version = "20240722.0.bcr.2")
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bazel_dep(name = "googletest", version = "1.15.2")
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bazel_dep(name = "rapidjson", version = "1.1.0.bcr.20241007")
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## C/C++ deps from local registry.
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bazel_dep(name = "prjxray", version = "0.0-583-t1e53270")
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git_override(
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module_name = "prjxray",
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commit = "3a95169e555de315c6b4cb71249107972d944303",
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patch_strip = 1,
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patches = ["//bazel:prjxray-add-module-bazel.patch"],
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remote = "https://github.com/f4pga/prjxray.git",
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)
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bazel_dep(name = "rules_license", version = "1.0.0")
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# compilation DB; build_cleaner
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bazel_dep(name = "bant", version = "0.1.14", dev_dependency = True)

‎README.md‎

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@@ -30,10 +30,6 @@ or install in system directory that requires root-access:
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sudo install -D --strip bazel-bin/fpga/fpga-as /usr/local/bin/fpga-as
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```
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[fasm-spec]: https://fasm.readthedocs.io/en/stable/#
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[bazel]: https://bazel.build/
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[counter-example]: https://github.com/chipsalliance/f4pga-examples/blob/13f11197b33dae1cde3bf146f317d63f0134eacf/xc7/counter_test/counter.v
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# How it works
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## Frames generation
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* offset: `77`
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Using this metadata, you can search the segbits database for the specific feature. By matching the tile_type and the FASM feature name, you can identify the correct configuration bits in the tile type segbits file (`segbits_clblm_r.db`). In this case, you would look for the entry corresponding to CLBLM_R.SLICEM_X0.ALUT.INIT and find the entry for address `[34]`. The value 34_06 then provides the coordinates for the word index and the specific bit index to be set.
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[fasm-spec]: https://fasm.readthedocs.io/en/stable/#
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[bazel]: https://bazel.build/
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[counter-example]: https://github.com/chipsalliance/f4pga-examples/blob/13f11197b33dae1cde3bf146f317d63f0134eacf/xc7/counter_test/counter.v

‎fpga/assembler.cc‎

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@@ -430,7 +430,7 @@ int main(int argc, char *argv[]) {
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<< '\n';
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return EXIT_FAILURE;
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}
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PrintFrames(frames, std::cout, false);
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// Write bitstream
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return EXIT_SUCCESS;
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}

‎fpga/database-parsers_test.cc‎

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#include "gtest/gtest.h"
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namespace fpga {
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template <typename Sink>
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void AbslStringify(Sink &sink, const TileFeature &e) {
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absl::Format(&sink, "(tile_feature=\"%s\", address=%d)", e.tile_feature,

‎fpga/xilinx/BUILD‎

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load("@rules_cc//cc:defs.bzl", "cc_library", "cc_test")
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load("@rules_license//rules:license.bzl", "license")
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package(
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default_applicable_licenses = [":license"],
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default_visibility = ["//:__subpackages__"],
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)
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license(
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name = "license",
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package_name = "xilinx",
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license_kind = "@rules_license//licenses/spdx:ISC",
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license_text = "LICENSE",
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)
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cc_library(
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name = "big-endian-span",
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hdrs = [
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"big-endian-span.h",
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],
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deps = [
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"@abseil-cpp//absl/types:span",
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],
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)
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cc_test(
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name = "big-endian-span_test",
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srcs = [
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"big-endian-span_test.cc",
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],
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deps = [
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":big-endian-span",
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"@googletest//:gtest",
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"@googletest//:gtest_main",
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],
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)
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cc_library(
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name = "bit-ops",
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hdrs = [
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"bit-ops.h",
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],
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)
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cc_test(
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name = "bit-ops_test",
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srcs = [
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"bit-ops_test.cc",
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],
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deps = [
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":bit-ops",
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"@googletest//:gtest",
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"@googletest//:gtest_main",
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],
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)
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cc_library(
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name = "architecture-xc7",
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srcs = [
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"architecture-xc7.cc",
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],
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hdrs = [
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"architecture-xc7.h",
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],
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deps = [
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":bit-ops",
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":configuration-packet",
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"@abseil-cpp//absl/types:span",
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],
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)
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cc_library(
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name = "configuration-packet",
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hdrs = [
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"configuration-packet.h",
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],
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deps = [
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"@abseil-cpp//absl/types:optional",
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"@abseil-cpp//absl/types:span",
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],
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)

‎fpga/xilinx/README.md‎

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# Xilinx Bitstream Generation
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Most of this code originates from [prjxray][prjxray]. It was imported into this repository to simplify type interfacing and eliminate the dependency on yaml-cpp, which requires exceptions to be enabled.
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[prjxray]: https://github.com/f4pga/prjxray/tree/faf9c774a340e39cf6802d009996ed6016e63521/lib

‎fpga/xilinx/architecture-xc7.cc‎

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#include "architecture-xc7.h"
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#include <cstdint>
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#include <optional>
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#include <ostream>
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#include "absl/types/span.h"
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#include "fpga/xilinx/bit-ops.h"
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#include "fpga/xilinx/configuration-packet.h"
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namespace fpga {
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namespace xilinx {
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namespace xc7 {
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std::ostream &operator<<(std::ostream &o, const ConfigurationRegister &value) {
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switch (value) {
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case ConfigurationRegister::kCRC: return o << "CRC";
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case ConfigurationRegister::kFAR: return o << "Frame Address";
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case ConfigurationRegister::kFDRI: return o << "Frame Data Input";
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case ConfigurationRegister::kFDRO: return o << "Frame Data Output";
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case ConfigurationRegister::kCMD: return o << "Command";
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case ConfigurationRegister::kCTL0: return o << "Control 0";
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case ConfigurationRegister::kMASK: return o << "Mask for CTL0 and CTL1";
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case ConfigurationRegister::kSTAT: return o << "Status";
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case ConfigurationRegister::kLOUT: return o << "Legacy Output";
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case ConfigurationRegister::kCOR0: return o << "Configuration Option 0";
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case ConfigurationRegister::kMFWR: return o << "Multiple Frame Write";
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case ConfigurationRegister::kCBC: return o << "Initial CBC Value";
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case ConfigurationRegister::kIDCODE: return o << "Device ID";
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case ConfigurationRegister::kAXSS: return o << "User Access";
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case ConfigurationRegister::kCOR1: return o << "Configuration Option 1";
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case ConfigurationRegister::kWBSTAR: return o << "Warm Boot Start Address";
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case ConfigurationRegister::kTIMER: return o << "Watchdog Timer";
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case ConfigurationRegister::kBOOTSTS: return o << "Boot History Status";
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case ConfigurationRegister::kCTL1: return o << "Control 1";
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case ConfigurationRegister::kBSPI:
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return o << "BPI/SPI Configuration Options";
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default: return o << "Unknown";
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}
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}
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ConfigurationPacket::ParseResult ConfigurationPacket::InitWithWordsImpl(
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absl::Span<uint32_t> words, const ConfigurationPacket *previous_packet) {
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using ConfigurationRegister = ConfigurationRegister;
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// Need at least one 32-bit word to have a valid packet header.
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if (words.empty() < 1) {
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return {words, {}};
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}
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const ConfigurationPacketType header_type =
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static_cast<ConfigurationPacketType>(bit_field_get(words[0], 31, 29));
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switch (header_type) {
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case ConfigurationPacketType::kNONE:
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// Type 0 is emitted at the end of a configuration row
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// when BITSTREAM.GENERAL.DEBUGBITSTREAM is set to YES.
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// These seem to be padding that are interepreted as
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// NOPs. Since Type 0 packets don't exist according to
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// UG470 and they seem to be zero-filled, just consume
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// the bytes without generating a packet.
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return {words.subspan(1),
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{{static_cast<uint32_t>(header_type),
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Opcode::kNOP,
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ConfigurationRegister::kCRC,
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{}}}};
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case ConfigurationPacketType::kTYPE1: {
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const Opcode opcode = static_cast<Opcode>(bit_field_get(words[0], 28, 27));
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const ConfigurationRegister address =
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static_cast<ConfigurationRegister>(bit_field_get(words[0], 26, 13));
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const uint32_t data_word_count = bit_field_get(words[0], 10, 0);
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// If the full packet has not been received, return as
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// though no valid packet was found.
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if (data_word_count > words.size() - 1) {
72+
return {words, {}};
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}
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return {words.subspan(data_word_count + 1),
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{{static_cast<uint32_t>(header_type), opcode, address,
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words.subspan(1, data_word_count)}}};
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}
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case ConfigurationPacketType::kTYPE2: {
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std::optional<ConfigurationPacket> packet;
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const Opcode opcode = static_cast<Opcode>(bit_field_get(words[0], 28, 27));
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const uint32_t data_word_count = bit_field_get(words[0], 26, 0);
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// If the full packet has not been received, return as
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// though no valid packet was found.
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if (data_word_count > words.size() - 1) {
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return {words, {}};
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}
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if (previous_packet) {
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packet = ConfigurationPacket(static_cast<uint32_t>(header_type), opcode,
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previous_packet->address(),
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words.subspan(1, data_word_count));
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}
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return {words.subspan(data_word_count + 1), packet};
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}
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default: return {{}, {}};
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}
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}
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} // namespace xc7
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} // namespace xilinx
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} // namespace fpga

‎fpga/xilinx/architecture-xc7.h‎

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/*
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* Copyright (C) 2017-2020 The Project X-Ray Authors.
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*
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* Use of this source code is governed by a ISC-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/ISC
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*
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* SPDX-License-Identifier: ISC
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*/
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#ifndef FPGA_XILINX_ARCHITECTURE_H
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#define FPGA_XILINX_ARCHITECTURE_H
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#include <cstdint>
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#include <memory>
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#include <ostream>
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#include <vector>
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#include "absl/types/span.h"
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#include "fpga/xilinx/configuration-packet.h"
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namespace fpga {
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namespace xilinx {
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namespace xc7 {
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// Series-7 configuration register addresses
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// according to UG470, pg. 109
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enum class ConfigurationRegister : unsigned int {
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kCRC = 0x00,
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kFAR = 0x01,
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kFDRI = 0x02,
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kFDRO = 0x03,
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kCMD = 0x04,
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kCTL0 = 0x05,
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kMASK = 0x06,
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kSTAT = 0x07,
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kLOUT = 0x08,
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kCOR0 = 0x09,
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kMFWR = 0x0a,
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kCBC = 0x0b,
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kIDCODE = 0x0c,
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kAXSS = 0x0d,
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kCOR1 = 0x0e,
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kWBSTAR = 0x10,
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kTIMER = 0x11,
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kUNKNOWN = 0x13,
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kBOOTSTS = 0x16,
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kCTL1 = 0x18,
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kBSPI = 0x1F,
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};
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std::ostream &operator<<(std::ostream &o, const ConfigurationRegister &value);
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enum class Architecture {
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kBase,
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kUltrascale,
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kUltrascalePlus,
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};
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template <Architecture arch>
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struct frame_words_count;
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template <>
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struct frame_words_count<Architecture::kBase> {
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static constexpr int value = 101;
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};
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template <>
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struct frame_words_count<Architecture::kUltrascale> {
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static constexpr int value = 123;
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};
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template <>
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struct frame_words_count<Architecture::kUltrascalePlus> {
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static constexpr int value = 93;
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};
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template <Architecture arch>
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using frame_words_count_v = frame_words_count<arch>::value;
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struct Part {};
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class ConfigurationPacket
82+
: public ConfigurationPacketBase<ConfigurationRegister,
83+
ConfigurationPacket> {
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private:
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using BaseType =
86+
ConfigurationPacketBase<ConfigurationRegister, ConfigurationPacket>;
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public:
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using BaseType::BaseType;
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private:
92+
friend BaseType;
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static ParseResult InitWithWordsImpl(
94+
absl::Span<uint32_t> words,
95+
const ConfigurationPacket *previous_packet = nullptr);
96+
};
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using ConfigurationPackage = std::vector<std::unique_ptr<ConfigurationPacket>>;
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} // namespace xc7
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} // namespace xilinx
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} // namespace fpga
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#endif // FPGA_XILINX_ARCHITECTURE_H

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