[stm32] Add support for remapped A11/A12 pins on F0/G0

Author: chris-durand

src/modm/platform/gpio/stm32/module.lb

@@ -3,6 +3,7 @@
 #
 # Copyright (c) 2016-2018, Niklas Hauser
 # Copyright (c) 2017, Fabian Greif
+# Copyright (c) 2020, Christopher Durand
 #
 # This file is part of the modm project.
 #
@@ -123,6 +124,44 @@ def validate_alternate_functions(driver, env):
     if not success:
         env.log.debug("Gpio signal validation failed!")
 
+def is_remap_pin(driver, pin, port):
+    """
+    For the STM32F0/G0 series
+    -------------------------
+    Some chips exist where gpios can be multiplexed on some package pins
+    """
+    package_pins = driver["package"][0]["pin"]
+    pin_name = 'P{}{}'.format(port.upper(), pin)
+    package_pin = next(pin for pin in package_pins if pin['name'].startswith(pin_name))
+    variant = package_pin.get('variant', None)
+    if variant is not None and 'remap' in variant:
+        return True
+    else:
+        position = package_pin["position"]
+        def is_other_mapping(p):
+            variant = p.get('variant', None)
+            return (p['position'] == position) and variant is not None and 'remap' in variant
+        return any(pin for pin in package_pins if is_other_mapping(pin))
+
+def get_remap_command(family, pin, port):
+    if family not in ["f0", "g0"]:
+        raise ValidateException("Remapped package pins only supported for F0 and G0")
+    if (port != 'a' or pin not in ["9","10","11","12"]):
+        raise ValidateException("Only Pins PA9/PA10/PA11/PA12 can be remapped")
+
+    reg = 'SYSCFG->CFGR1'
+    value = {
+        ('f0', '9')  : ('SYSCFG_CFGR1_PA11_PA12_RMP', False),
+        ('f0', '10') : ('SYSCFG_CFGR1_PA11_PA12_RMP', False),
+        ('f0', '11') : ('SYSCFG_CFGR1_PA11_PA12_RMP', True),
+        ('f0', '12') : ('SYSCFG_CFGR1_PA11_PA12_RMP', True),
+        ('g0', '9')  : ('SYSCFG_CFGR1_PA11_RMP',      True),
+        ('g0', '10') : ('SYSCFG_CFGR1_PA12_RMP',      True),
+        ('g0', '11') : ('SYSCFG_CFGR1_PA11_RMP',      False),
+        ('g0', '12') : ('SYSCFG_CFGR1_PA12_RMP',      False)
+    }
+    return (reg,) + value[(family, pin)]
+
 bprops = {}
 
 # -----------------------------------------------------------------------------
@@ -257,6 +296,10 @@ def build(env):
 
     for gpio in driver["gpio"]:
         po, pi = gpio["port"], gpio["pin"]
+        properties["remap_pin"] = is_remap_pin(driver, pi, po)
+        if properties["remap_pin"]:
+            family = device.identifier["family"]
+            (properties["remap_reg"],properties["remap_value"],properties["remap_set"]) = get_remap_command(family, pi, po)
         properties.update(bprops[po + pi])
         header_name = "gpio_{}{}.hpp".format(po.upper(), pi)
         env.template(gpio_source, header_name, filters={ "to_adc_channel" : lambda name : "".join(filter(str.isdigit, name)) })

src/modm/platform/gpio/stm32/pin.hpp.in

@@ -74,6 +74,17 @@ public:
 	inline static void setAnalogInput() { PinSet::setAnalogInput(); }
 	/// @endcond
 
+%% if remap_pin
+	/// Remap this GPIO onto physical pins with selectable GPIO mappings
+	inline static void remap() {
+	%% if remap_set
+		{{remap_reg}} |= {{remap_value}};
+	%% else
+		{{remap_reg}} &= ~{{remap_value}};
+	%% endif
+	};
+%% endif
+
 public:
 	// GpioOutput
 	// start documentation inherited