Multi-Tenant Behavior and Resource Sharing on Intel NPU4 #105
Description
Hi, I'm profiling workloads on the Intel NPU4 architecture and have some questions regarding multi-tenant usage.
The manual mentions 6 tiles with corresponding CMX. My main concern is how different users or processes share the NPU. Specifically:
Can multiple users/processes utilize different NPU tiles concurrently? Or is the NPU shared via time-division multiplexing?
If concurrent tile usage is possible, how is the SHAVE L2 Cache shared among them?
Is the scheduling of different users handled by hardware or software?
Understanding these aspects is crucial for optimizing our workload deployment. Any insights would be greatly appreciated.