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olvaffeMarge Bot
olvaffe
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freedreno/registers: document more bits of CP_REG_TEST
On gen3+, there are 32 predicate bits instead of 1. I set out to see why CP_REG_TEST (and others commands that read registers) is slower on gen1 but could not find anything. Since the blob seems to use multiple predicate bits, let's keep them documented. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21206>
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‎src/freedreno/.gitlab-ci/reference/crash.log‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3048,7 +3048,7 @@ indexed-registers:
30483048
00000000 0x17c: 00000000
30493049
00000000 0x17d: 00000000
30503050
00000000 0x17e: 00000000
3051-
00000000 0x17f: 00000000
3051+
00000000 PRED_REG: 0
30523052
- regs-name: CP_ROQ
30533053
dwords: 1024
30543054
-----------------------------------------------

‎src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -435,7 +435,7 @@ cmdstream[0]: 265 dwords
435435
ibaddr:000000000115e000
436436
ibsize:000000f1
437437
opcode: CP_COND_REG_EXEC (47) (3 dwords)
438-
{ REG0 = 0 | GMEM | MODE = RENDER_MODE }
438+
{ REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
439439
{ DWORDS = 23 }
440440
000000000115e000: 0000: 70c70002 34000000 00000017
441441
write RB_BLIT_SCISSOR_TL (88d1)
@@ -495,7 +495,7 @@ cmdstream[0]: 265 dwords
495495
RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
496496
000000000115e05c: 0000: 4888d102 00000000 00ff00ff
497497
opcode: CP_COND_REG_EXEC (47) (3 dwords)
498-
{ REG0 = 0 | SYSMEM | MODE = RENDER_MODE }
498+
{ REG0 = 0 | PRED_BIT = 0 | SYSMEM | MODE = RENDER_MODE }
499499
{ DWORDS = 0 }
500500
000000000115e068: 0000: 70c70002 38000000 00000000
501501
write RB_DEPTH_BUFFER_INFO (8872)
@@ -555,7 +555,7 @@ cmdstream[0]: 265 dwords
555555
RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
556556
000000000115e128: 0000: 4088d501 00000000
557557
opcode: CP_COND_REG_EXEC (47) (3 dwords)
558-
{ REG0 = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
558+
{ REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
559559
{ DWORDS = 4 }
560560
000000000115e130: 0000: 70c70002 3c000000 00000004
561561
opcode: CP_REG_WRITE (6d) (4 dwords)

‎src/freedreno/.gitlab-ci/reference/fd-clouds.log‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1471,10 +1471,10 @@ cmdstream[0]: 1023 dwords
14711471
gpuaddr:0000000001d90010
14721472
0000000001d918e0: 0000: 70c28003 00000883 01d90010 00000000
14731473
opcode: CP_REG_TEST (39) (2 dwords)
1474-
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
1474+
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
14751475
0000000001d918f0: 0000: 70b90001 02000883
14761476
opcode: CP_COND_REG_EXEC (47) (3 dwords)
1477-
{ REG0 = 0 | MODE = PRED_TEST }
1477+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
14781478
{ DWORDS = 7 }
14791479
0000000001d918f8: 0000: 70c70002 10000000 00000007
14801480
opcode: CP_REG_TO_MEM (3e) (4 dwords)
@@ -1553,10 +1553,10 @@ cmdstream[0]: 1023 dwords
15531553
opcode: CP_SET_MODE (63) (2 dwords)
15541554
0000000001d919d0: 0000: 70e30001 00000000
15551555
opcode: CP_REG_TEST (39) (2 dwords)
1556-
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
1556+
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
15571557
0000000001d919d8: 0000: 70b90001 02000883
15581558
opcode: CP_COND_REG_EXEC (47) (3 dwords)
1559-
{ REG0 = 0 | MODE = PRED_TEST }
1559+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
15601560
{ DWORDS = 11 }
15611561
0000000001d919e0: 0000: 70c70002 10000000 0000000b
15621562
opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
@@ -1703,10 +1703,10 @@ cmdstream[0]: 1023 dwords
17031703
:0,1,17,6
17041704
0000000001d91aa4: 0000: 48088901 00000011
17051705
opcode: CP_REG_TEST (39) (2 dwords)
1706-
{ REG = 0xc38 | BIT = 0 | SKIP_WAIT_FOR_ME }
1706+
{ REG = 0xc38 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
17071707
0000000001d91aac: 0000: 70b90001 02000c38
17081708
opcode: CP_COND_REG_EXEC (47) (3 dwords)
1709-
{ REG0 = 0 | MODE = PRED_TEST }
1709+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
17101710
{ DWORDS = 4 }
17111711
0000000001d91ab4: 0000: 70c70002 10000000 00000004
17121712
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
@@ -6745,10 +6745,10 @@ cmdstream[0]: 1023 dwords
67456745
:0,1,18,3
67466746
0000000001d91ad4: 0000: 48088901 00000012
67476747
opcode: CP_REG_TEST (39) (2 dwords)
6748-
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
6748+
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
67496749
0000000001d91adc: 0000: 70b90001 02000883
67506750
opcode: CP_COND_REG_EXEC (47) (3 dwords)
6751-
{ REG0 = 0 | MODE = PRED_TEST }
6751+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
67526752
{ DWORDS = 2 }
67536753
0000000001d91ae4: 0000: 70c70002 10000000 00000002
67546754
opcode: CP_SET_MARKER (65) (2 dwords)
@@ -6870,10 +6870,10 @@ cmdstream[0]: 1023 dwords
68706870
opcode: CP_SET_MODE (63) (2 dwords)
68716871
0000000001d91b9c: 0000: 70e30001 00000000
68726872
opcode: CP_REG_TEST (39) (2 dwords)
6873-
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
6873+
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
68746874
0000000001d91ba4: 0000: 70b90001 02000883
68756875
opcode: CP_COND_REG_EXEC (47) (3 dwords)
6876-
{ REG0 = 0 | MODE = PRED_TEST }
6876+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
68776877
{ DWORDS = 11 }
68786878
0000000001d91bac: 0000: 70c70002 10000000 0000000b
68796879
opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
@@ -6944,10 +6944,10 @@ cmdstream[0]: 1023 dwords
69446944
:0,1,27,24
69456945
0000000001d91c70: 0000: 48088901 0000001b
69466946
opcode: CP_REG_TEST (39) (2 dwords)
6947-
{ REG = 0xc39 | BIT = 0 | SKIP_WAIT_FOR_ME }
6947+
{ REG = 0xc39 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
69486948
0000000001d91c78: 0000: 70b90001 02000c39
69496949
opcode: CP_COND_REG_EXEC (47) (3 dwords)
6950-
{ REG0 = 0 | MODE = PRED_TEST }
6950+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
69516951
{ DWORDS = 4 }
69526952
0000000001d91c80: 0000: 70c70002 10000000 00000004
69536953
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
@@ -6961,10 +6961,10 @@ cmdstream[0]: 1023 dwords
69616961
:0,1,28,24
69626962
0000000001d91ca0: 0000: 48088901 0000001c
69636963
opcode: CP_REG_TEST (39) (2 dwords)
6964-
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
6964+
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
69656965
0000000001d91ca8: 0000: 70b90001 02000883
69666966
opcode: CP_COND_REG_EXEC (47) (3 dwords)
6967-
{ REG0 = 0 | MODE = PRED_TEST }
6967+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
69686968
{ DWORDS = 2 }
69696969
0000000001d91cb0: 0000: 70c70002 10000000 00000002
69706970
opcode: CP_SET_MARKER (65) (2 dwords)
@@ -7039,10 +7039,10 @@ cmdstream[0]: 1023 dwords
70397039
opcode: CP_SET_MODE (63) (2 dwords)
70407040
0000000001d91d68: 0000: 70e30001 00000000
70417041
opcode: CP_REG_TEST (39) (2 dwords)
7042-
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
7042+
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
70437043
0000000001d91d70: 0000: 70b90001 02000883
70447044
opcode: CP_COND_REG_EXEC (47) (3 dwords)
7045-
{ REG0 = 0 | MODE = PRED_TEST }
7045+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
70467046
{ DWORDS = 11 }
70477047
0000000001d91d78: 0000: 70c70002 10000000 0000000b
70487048
opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
@@ -7113,10 +7113,10 @@ cmdstream[0]: 1023 dwords
71137113
:0,1,37,34
71147114
0000000001d91e3c: 0000: 48088901 00000025
71157115
opcode: CP_REG_TEST (39) (2 dwords)
7116-
{ REG = 0xc3a | BIT = 0 | SKIP_WAIT_FOR_ME }
7116+
{ REG = 0xc3a | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
71177117
0000000001d91e44: 0000: 70b90001 02000c3a
71187118
opcode: CP_COND_REG_EXEC (47) (3 dwords)
7119-
{ REG0 = 0 | MODE = PRED_TEST }
7119+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
71207120
{ DWORDS = 4 }
71217121
0000000001d91e4c: 0000: 70c70002 10000000 00000004
71227122
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
@@ -7130,10 +7130,10 @@ cmdstream[0]: 1023 dwords
71307130
:0,1,38,34
71317131
0000000001d91e6c: 0000: 48088901 00000026
71327132
opcode: CP_REG_TEST (39) (2 dwords)
7133-
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
7133+
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
71347134
0000000001d91e74: 0000: 70b90001 02000883
71357135
opcode: CP_COND_REG_EXEC (47) (3 dwords)
7136-
{ REG0 = 0 | MODE = PRED_TEST }
7136+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
71377137
{ DWORDS = 2 }
71387138
0000000001d91e7c: 0000: 70c70002 10000000 00000002
71397139
opcode: CP_SET_MARKER (65) (2 dwords)
@@ -7208,10 +7208,10 @@ cmdstream[0]: 1023 dwords
72087208
opcode: CP_SET_MODE (63) (2 dwords)
72097209
0000000001d91f34: 0000: 70e30001 00000000
72107210
opcode: CP_REG_TEST (39) (2 dwords)
7211-
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
7211+
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
72127212
0000000001d91f3c: 0000: 70b90001 02000883
72137213
opcode: CP_COND_REG_EXEC (47) (3 dwords)
7214-
{ REG0 = 0 | MODE = PRED_TEST }
7214+
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
72157215
{ DWORDS = 11 }
72167216
0000000001d91f44: 0000: 70c70002 10000000 0000000b
72177217
opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)

‎src/freedreno/registers/adreno/adreno_control_regs.xml‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -223,6 +223,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
223223
<reg32 name="SCRATCH_REG5" offset="0x175"/>
224224
<reg32 name="SCRATCH_REG6" offset="0x176"/>
225225
<reg32 name="SCRATCH_REG7" offset="0x177"/>
226+
227+
<!-- new in gen3+ -->
228+
<reg32 name="PRED_REG" offset="0x17f"/>
226229
</domain>
227230

228231
</database>

‎src/freedreno/registers/adreno/adreno_pm4.xml‎

Lines changed: 15 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1723,14 +1723,20 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
17231723
<bitfield name="BIT" low="20" high="24" type="uint"/>
17241724
<!-- skip implied CP_WAIT_FOR_ME -->
17251725
<bitfield name="SKIP_WAIT_FOR_ME" pos="25" type="boolean"/>
1726-
<!--
1727-
Appears only in:
1728-
opcode: CP_REG_TEST (39) (4 dwords)
1729-
{ REG = 0 | BIT = 0 | WAIT_FOR_ME | UNK31 }
1730-
Seem to force CP_REG_TEST to write false
1731-
-->
1732-
<bitfield name="UNK31" pos="31" type="boolean"/>
1726+
<!-- the predicate bit to set (new in gen3+) -->
1727+
<bitfield name="PRED_BIT" low="26" high="30" type="uint"/>
1728+
<!-- update the predicate reg directly (new in gen3+) -->
1729+
<bitfield name="PRED_UPDATE" pos="31" type="boolean"/>
17331730
</reg32>
1731+
1732+
<!--
1733+
In PRED_UPDATE mode, the predicate reg is updated directly using two
1734+
more dwords, ignoring other bits:
1735+
1736+
PRED_REG = (PRED_REG & ~PRED_MASK) | (PRED_VAL & PRED_MASK);
1737+
-->
1738+
<reg32 offset="1" name="PRED_MASK" type="hex"/>
1739+
<reg32 offset="2" name="PRED_VAL" type="hex"/>
17341740
</domain>
17351741

17361742
<!-- I *think* this existed at least as far back as a4xx -->
@@ -1746,15 +1752,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
17461752
<reg32 offset="0" name="0">
17471753
<bitfield name="REG0" low="0" high="17" type="hex"/>
17481754

1749-
<!--
1750-
Blob uses them for vkCmdClearAttachments in gmem mode. Examples:
1751-
opcode: CP_COND_REG_EXEC (47) (3 dwords)
1752-
{ REG0 = 0 | MODE = PRED_TEST | 0x140000 }
1753-
opcode: CP_COND_REG_EXEC (47) (3 dwords)
1754-
{ REG0 = 0 | MODE = PRED_TEST | 0x100000 }
1755-
-->
1756-
<bitfield name="UNK18" pos="18" varset="chip" variants="A6XX-" type="boolean"/>
1757-
<bitfield name="UNK20" pos="20" varset="chip" variants="A6XX-" type="boolean"/>
1755+
<!-- the predicate bit to test (new in gen3+) -->
1756+
<bitfield name="PRED_BIT" low="18" high="22" varset="chip" variants="A6XX-" type="uint"/>
17581757

17591758
<!--
17601759
Note: these bits have the same meaning, and use the same

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