SPI: SCLK polarity (CPOL) is inverted #1583
Description
(derived from earlephilhower/arduino-pico#1900)
so for CPOL = 0, the SCLK pin should idle LOW before and after a SPI transfer.
However, testing with
#include <hardware/spi.h>
static int _sck = 2;
static int _mosi = 3;
static int _miso = 4;
static int _cs = 5;
static spi_inst_t* _spi = spi0;
int main(){
gpio_set_function(_sck, GPIO_FUNC_SPI);
gpio_set_function(_mosi, GPIO_FUNC_SPI);
gpio_set_function(_miso, GPIO_FUNC_SPI);
gpio_set_function(_cs, GPIO_FUNC_SPI);
spi_init(_spi, 100000);
spi_set_format(_spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
while(1) {
uint8_t value = 0xAA;
(void) spi_write_blocking(_spi, &value, sizeof(value));
delay(100);
}
return 0;
}I see
on GP2, 3, 4 and 5 respectively. This is exactly inverted, it idles HIGH. Wut?
Note that changing to SPI_CPOL_1 in the above example will make the clock idle low, which is again opposite to how it should be. No matter what, in my logic analyzer, I always have to select the opposite SPI mode / clock polarity than what I set in the code to make it decodable.
