@@ -824,8 +824,10 @@ void set_interrupt(int dev, int lvl) {
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dev_irq [dev >>2 ] = 0200 >> lvl ;
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#endif
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pi_pending = 1 ;
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+ #if DEBUG
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sim_debug (DEBUG_IRQ , & cpu_dev , "set irq %o %o %03o %03o %03o\n" ,
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dev & 0774 , lvl , PIE , PIR , PIH );
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+ #endif
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}
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}
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@@ -837,8 +839,10 @@ void set_interrupt_mpx(int dev, int lvl, int mpx) {
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if (lvl == 1 && mpx != 0 )
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dev_irq [dev >>2 ] |= mpx << 8 ;
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pi_pending = 1 ;
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+ #if DEBUG
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sim_debug (DEBUG_IRQ , & cpu_dev , "set mpx irq %o %o %o %03o %03o %03o\n" ,
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dev & 0774 , lvl , mpx , PIE , PIR , PIH );
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+ #endif
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}
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}
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#endif
@@ -848,8 +852,10 @@ void set_interrupt_mpx(int dev, int lvl, int mpx) {
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*/
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void clr_interrupt (int dev ) {
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dev_irq [dev >>2 ] = 0 ;
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+ #if DEBUG
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if (dev > 4 )
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sim_debug (DEBUG_IRQ , & cpu_dev , "clear irq %o\n" , dev & 0774 );
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+ #endif
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}
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/*
@@ -930,7 +936,9 @@ void restore_pi_hold() {
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for (lvl = 0100 ; lvl != 0 ; lvl >>= 1 ) {
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if (lvl & PIH ) {
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PIR &= ~lvl ;
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+ #if DEBUG
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sim_debug (DEBUG_IRQ , & cpu_dev , "restore irq %o %03o\n" , lvl , PIH );
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+ #endif
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PIH &= ~lvl ;
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break ;
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}
@@ -4594,8 +4602,10 @@ if ((reason = build_dev_tab ()) != SCPE_OK) /* build, chk dib_tab */
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#if KA | PDP6
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st_pi :
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#endif
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+ #if DEBUG
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sim_debug (DEBUG_IRQ , & cpu_dev , "trap irq %o %03o %03o \n" ,
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pi_enc , PIR , PIH );
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+ #endif
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pi_cycle = 1 ;
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pi_rq = 0 ;
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pi_hold = 0 ;
@@ -4614,7 +4624,9 @@ if ((reason = build_dev_tab ()) != SCPE_OK) /* build, chk dib_tab */
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if (new_lvl != 0 )
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pi_pending = 1 ;
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}
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+ #if DEBUG
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sim_debug (DEBUG_IRQ , & cpu_dev , "vect irq %o %06o\n" , pi_enc , AB );
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+ #endif
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}
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goto fetch ;
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#endif
@@ -4626,8 +4638,10 @@ if ((reason = build_dev_tab ()) != SCPE_OK) /* build, chk dib_tab */
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for (f = 0 ; f < MAX_DEV ; f ++ ) {
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if (dev_irqv [f ] != 0 && dev_irq [f ] & pi_mask ) {
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AB = dev_irqv [f ](f << 2 , AB );
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+ #if DEBUG
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sim_debug (DEBUG_IRQ , & cpu_dev , "vect irq %o %03o %06o\n" ,
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pi_enc , dev_irq [f ], AB );
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+ #endif
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break ;
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}
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}
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