2-slots TDD period

[improperaffo]

Dear all,
Has anybody ever successfully run a TDD pattern with only 2 slots (i.e., 1ms in numerology 1)?

So far, we have tried:

1. 1D and 1U (DU)
   Which does not work because you need to have space for a mixed (M) slot in the pattern.
2. 1D and 1M (DM)
   Which we could not get to work because of the following assertion
   

   Assertion `idx_found.has_value()' failed - Unable to find a PRACH config index for the given TDD pattern
   

3. 1M and 1 U (MU)
   Which does not work because of the following assertion
   

   srsRAN FATAL ERROR: PDCCH slot is not DL enabled.
   

Did anybody manage to get away with a pattern of 2 slots only?
Thanks

[dmd17]

for more context, we are trying to run SRS with a DUDU TDD pattern.

however, in SRS there must be a mixed slot, so we tried MU and DM, both did not work for different reasons.

in the first case, MU, the pattern is:
tdd_ul_dl_cfg:
nof_dl_slots: 0
nof_dl_symbols: 12
nof_ul_symbols: 0
nof_ul_slots: 1

in sib1_scheduler.cpp the assumption that SIB1 is always in the N+1 slot.
sib1_scheduler::sib1_scheduler(const cell_configuration& cfg_,
pdcch_resource_allocator& pdcch_sch,
units::bytes sib1_payload_size_) :
expert_cfg{cfg_.expert_cfg.si},
cell_cfg{cfg_},
pdcch_sched{pdcch_sch},
coreset0{cell_cfg.coreset0},
searchspace0{cell_cfg.searchspace0},
sib1_payload_size{sib1_payload_size_}
{
// Compute derived SIB1 parameters.
sib1_rtx_period = std::chrono::milliseconds{std::max(ssb_periodicity_to_value(cfg_.ssb_cfg.ssb_period),
sib1_rtx_periodicity_to_value(expert_cfg.sib1_retx_period))};

for (size_t i_ssb = 0; i_ssb < MAX_NUM_BEAMS; i_ssb++) {
if (not is_nth_ssb_beam_active(cell_cfg.ssb_cfg.ssb_bitmap, i_ssb)) {
continue;
}
// NOTE:
// - [Implementation defined] Use (n0 + 1) slot to avoid collisions between SSB and SIB1.
sib1_type0_pdcch_css_slots[i_ssb] =
precompute_type0_pdcch_css_n0_plus_1(searchspace0, coreset0, cell_cfg, cell_cfg.scs_common, i_ssb);
}

// Define a BWP configuration limited by CORESET#0 RBs.
coreset0_bwp_cfg = cell_cfg.dl_cfg_common.init_dl_bwp.generic_params;
coreset0_bwp_cfg.crbs = get_coreset0_crbs(cell_cfg.dl_cfg_common.init_dl_bwp.pdcch_common);
}

the following function is called by sib1_scheduler
slot_point srsran::precompute_type0_pdcch_css_n0_plus_1(uint8_t searchspace0,
uint8_t coreset0,
const cell_configuration& cell_cfg,
subcarrier_spacing scs_common,
unsigned ssb_index)
{
const auto pdcch_slot = precompute_type0_pdcch_css_n0(searchspace0, coreset0, cell_cfg, scs_common, ssb_index) + 1;
report_fatal_error_if_not(cell_cfg.is_dl_enabled(pdcch_slot), "PDCCH slot is not DL enabled +1.");
return pdcch_slot;
}

in this case, dl_symbols_per_slot_lst has 2 entries.
dl_symbols_per_slot_lst[0] == 12
dl_symbols_per_slot_lst[1] == 0

there are probably enough symbols in the slot for SSB, CORESET#0, and PDCCH
SSB is 4 symbols long
CORESET is max 3 symbols long
that leaves 5 symbols...
it is possible that it fits

we can try to call precompute_type0_pdcch_css_n0 and see what happens.
I believe that's legal.

AFAIK, it is legal to schedule CORESET and PDCCH in a subsequent slot.

if we set the pattern to:
tdd_ul_dl_cfg:
nof_dl_slots: 0
nof_dl_symbols: 12
nof_ul_symbols: 0
nof_ul_slots: 1
pattern2:
dl_ul_tx_period: 2
nof_dl_slots: 0
nof_dl_symbols: 12
nof_ul_symbols: 0
nof_ul_slots: 1

then dl_symbols_per_slot_lst has 4 entries:
dl_symbols_per_slot_lst[0] == 12
dl_symbols_per_slot_lst[1] == 0
dl_symbols_per_slot_lst[2] == 12
dl_symbols_per_slot_lst[3] == 0

we also tried scheduling SIB1 in N+2:
that is a hack specifically for the MUMU pattern.

however, the phone does not connect...

what are we misunderstanding?