Possible typo in maximal frequency.

[matoushybl]

There are two different frequencies mentioned in the comments and in the code.

stm32f7xx-hal/src/rcc.rs

Lines 468 to 476 in 0a0d06d

	let mut pclk1: u32 = min(max_pclk1, self.pclk1.unwrap_or(hclk));
	// PCLK2 (APB2). Must be <= 108 Mhz. By default, min(hclk, 108Mhz) is
	// chosen
	// Add limits dependens on OD follows by DS Table 16.
	let max_pclk2 = if sysclk <= 180_000_000 {
	90_000_000
	} else {
	108_000_000
	};

[hannobraun]

Thank you, good catch! Just from reading the code, it's not clear to me whether this is actually wrong, but it definitely looks dubious.

Even it this doesn't need fixing, a better comment would be great.

[matoushybl]

Oh, I see it now. Sorry for the mistake, I agree with adding a slightly improved comment, but I believe we could also extract the frequencies for example to a module with constants.