Update for staging PAC 0.17.0 (#28)

usbalbin · web-flow · commit 86ec4c5bde81 · 2025-01-06T15:41:11.000-08:00
diff --git a/Cargo.toml b/Cargo.toml
@@ -44,7 +44,7 @@ log-semihost = ["log"]
 
 [dependencies]
 cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] }
-stm32h5 = "0.15.1"
+stm32h5 = { package = "stm32h5-staging", version = "0.17.0" }
 fugit = "0.3.7"
 embedded-hal = "1.0.0"
 defmt = { version = "0.3.8", optional = true }
diff --git a/src/gpio.rs b/src/gpio.rs
@@ -318,11 +318,9 @@ where
         let offset = 2 * { N };
 
         unsafe {
-            (*Gpio::<P>::ptr()).ospeedr().modify(|r, w| {
-                w.bits(
-                    (r.bits() & !(0b11 << offset)) | ((speed as u32) << offset),
-                )
-            });
+            (*Gpio::<P>::ptr())
+                .ospeedr()
+                .modify(|_r, w| w.ospeed(offset).bits(speed as u8));
         }
     }
 
@@ -340,11 +338,11 @@ where
     /// Set the internal pull-up and pull-down resistor
     pub fn set_internal_resistor(&mut self, resistor: Pull) {
         let offset = 2 * { N };
-        let value = resistor as u32;
+        let value = resistor as u8;
         unsafe {
-            (*Gpio::<P>::ptr()).pupdr().modify(|r, w| {
-                w.bits((r.bits() & !(0b11 << offset)) | (value << offset))
-            });
+            (*Gpio::<P>::ptr())
+                .pupdr()
+                .modify(|_r, w| w.pupd(offset).bits(value));
         }
     }
 
@@ -428,22 +426,26 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {
     #[inline(always)]
     fn _set_high(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
-        unsafe { (*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << N)) }
+        unsafe {
+            (*Gpio::<P>::ptr()).bsrr().write(|w| w.bs(N).set_bit());
+        }
     }
     #[inline(always)]
     fn _set_low(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
-        unsafe { (*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << (16 + N))) }
+        unsafe {
+            (*Gpio::<P>::ptr()).bsrr().write(|w| w.br(N).set_bit());
+        }
     }
     #[inline(always)]
     fn _is_set_low(&self) -> bool {
         // NOTE(unsafe) atomic read with no side effects
-        unsafe { (*Gpio::<P>::ptr()).odr().read().bits() & (1 << N) == 0 }
+        unsafe { (*Gpio::<P>::ptr()).odr().read().od(N).is_low() }
     }
     #[inline(always)]
     fn _is_low(&self) -> bool {
         // NOTE(unsafe) atomic read with no side effects
-        unsafe { (*Gpio::<P>::ptr()).idr().read().bits() & (1 << N) == 0 }
+        unsafe { (*Gpio::<P>::ptr()).idr().read().id(N).is_low() }
     }
 }
 
diff --git a/src/gpio/exti.rs b/src/gpio/exti.rs
@@ -142,7 +142,7 @@ where
                 Edge::Rising => exti.rpr1().write(|w| w.bits(mask)),
                 Edge::Falling => exti.fpr1().write(|w| w.bits(mask)),
                 _ => panic!("Must choose a rising or falling edge"),
-            }
+            };
         }
     }
 
diff --git a/src/gpio/partially_erased.rs b/src/gpio/partially_erased.rs
@@ -62,17 +62,17 @@ impl<const P: char, MODE> PartiallyErasedPin<P, Output<MODE>> {
     #[inline(always)]
     pub fn set_high(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
-        unsafe { (*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << self.i)) }
+        unsafe {
+            (*Gpio::<P>::ptr()).bsrr().write(|w| w.bs(self.i).set_bit());
+        }
     }
 
     /// Drives the pin low
     #[inline(always)]
     pub fn set_low(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
         unsafe {
-            (*Gpio::<P>::ptr())
-                .bsrr()
-                .write(|w| w.bits(1 << (self.i + 16)))
+            (*Gpio::<P>::ptr()).bsrr().write(|w| w.br(self.i).set_bit());
         }
     }
 
diff --git a/src/rcc.rs b/src/rcc.rs
@@ -685,11 +685,11 @@ impl Rcc {
             w.mco1sel()
                 .variant(self.config.mco1.source)
                 .mco1pre()
-                .bits(mco_1_pre)
+                .set(mco_1_pre)
                 .mco2sel()
                 .variant(self.config.mco2.source)
                 .mco2pre()
-                .bits(mco_2_pre)
+                .set(mco_2_pre)
         });
 
         // HSE
@@ -747,7 +747,7 @@ impl Rcc {
 
         // Ensure core prescaler value is valid before future lower
         // core voltage
-        while rcc.cfgr2().read().hpre().variant() != Some(hpre_bits) {}
+        while rcc.cfgr2().read().hpre().variant() != hpre_bits {}
 
         // Peripheral Clock (per_ck)
         rcc.ccipr5().modify(|_, w| w.ckpersel().variant(ckpersel));
@@ -805,10 +805,10 @@ impl Rcc {
             let cfgr2 = rcc.cfgr2().read();
             debug!(
                 "CFGR2 register: HPRE={:?} PPRE1={:?} PPRE2={:?} PPRE3={:?}",
-                cfgr2.hpre().variant().unwrap(),
-                cfgr2.ppre1().variant().unwrap(),
-                cfgr2.ppre2().variant().unwrap(),
-                cfgr2.ppre3().variant().unwrap(),
+                cfgr2.hpre().variant(),
+                cfgr2.ppre1().variant(),
+                cfgr2.ppre2().variant(),
+                cfgr2.ppre3().variant(),
             );
 
             let pll1cfgr = rcc.pll1cfgr().read();
diff --git a/src/rcc/pll.rs b/src/rcc/pll.rs
@@ -222,7 +222,7 @@ macro_rules! pll_divider_setup {
 
                     // Setup divider
                     $rcc.[<$pllX divr>]().modify(|_, w|
-                        w.[<$pllX $d>]().variant((pll_x_d.div - 1) as u8)
+                        w.[<$pllX $d>]().set((pll_x_d.div - 1) as u8)
                     );
                     $rcc.[<$pllX cfgr>]().modify(|_, w| w.[<$pllX $d en>]().enabled());
                     Some(Hertz::from_raw($vco_ck / pll_x_d.div))
@@ -262,14 +262,14 @@ macro_rules! pll_setup {
                 let pll_x_n = pll_setup.vco_out_target / pll_setup.ref_ck;
 
                 // Write dividers
-                rcc.[< $pllX cfgr >]().modify(|_, w|
+                rcc.[< $pllX cfgr >]().modify(|_, w| unsafe {
                     w.[< $pllX m >]()
-                    .variant(pll_setup.pll_m as u8));  // ref prescaler
+                    .bits(pll_setup.pll_m as u8) });  // ref prescaler
 
                 // unsafe as not all values are permitted: see RM0492
                 assert!(pll_x_n >= PLL_N_MIN);
                 assert!(pll_x_n <= PLL_N_MAX);
-                rcc.[<$pllX divr>]().modify(|_, w| w.[<$pllX n>]().variant((pll_x_n - 1) as u16));
+                rcc.[<$pllX divr>]().modify(|_, w| unsafe { w.[<$pllX n>]().bits((pll_x_n - 1) as u16) });
 
                 let pll_x = pll_setup.pll_p.as_ref().or(pll_setup.pll_q.as_ref().or(pll_setup.pll_r.as_ref())).unwrap();
 
@@ -279,10 +279,10 @@ macro_rules! pll_setup {
                         // Calculate FRACN
                         let pll_x_fracn = calc_fracn(pll_setup.ref_ck as f32, pll_x_n as f32, pll_x.div as f32, pll_x.ck as f32);
                         //RCC_PLL1FRACR
-                        rcc.[<$pllX fracr>]().modify(|_, w| w.[<$pllX fracn>]().variant(pll_x_fracn));
+                        rcc.[<$pllX fracr>]().modify(|_, w| w.[<$pllX fracn>]().set(pll_x_fracn));
                         // Latch FRACN by resetting and setting it
                         rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().reset() );
-                        rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().set() );
+                        rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().set_() );
 
                         calc_vco_ck(pll_setup.ref_ck, pll_x_n, pll_x_fracn)
                     },
diff --git a/src/rcc/rec.rs b/src/rcc/rec.rs
@@ -129,8 +129,8 @@ macro_rules! peripheral_reset_and_enable_control {
         $(
             $( #[ $pmeta:meta ] )*
                 $(($NoReset:ident))? $p:ident
-                $([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $ccip:ident $clk_doc:expr ])*
-                $([ group clk: $pk_g:ident $( $(($Variant_g:ident))* $ccip_g:ident $clk_doc_g:expr )* ])*
+                $([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $pk_alias:ident $ccip:ident $clk_doc:expr ])*
+                $([ group clk: $pk_g:ident $( $(($Variant_g:ident))* $pk_g_alias:ident $ccip_g:ident $clk_doc_g:expr )* ])*
                 $([ fixed clk: $clk_doc_f:expr ])*
         ),*
     ];)+) => {
@@ -177,10 +177,10 @@ macro_rules! peripheral_reset_and_enable_control {
                         $AXBn, $(($NoReset))* $p, [< $p:upper >], [< $p:lower >],
                         $( $pmeta )*
                         $(
-                            [kernel $clk: $pk $(($Variant))* $ccip $clk_doc]
+                            [kernel $clk: $pk $(($Variant))* $pk_alias $ccip $clk_doc]
                         )*
                         $(
-                            [group clk: $pk_g [< $pk_g:lower >] $( $(($Variant_g))* $ccip_g $clk_doc_g )* ]
+                            [group clk: $pk_g [< $pk_g:lower >] $( $(($Variant_g))* $pk_g_alias $ccip_g $clk_doc_g )* ]
                         )*
                         $(
                             [fixed clk: $clk_doc_f]
@@ -230,8 +230,8 @@ macro_rules! peripheral_reset_and_enable_control_generator {
         $p_lower:ident,         // comments, equivalent to with the paste macro.
 
         $( $pmeta:meta )*
-        $([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $ccip:ident $clk_doc:expr ])*
-        $([ group clk: $pk_g:ident $pk_g_lower:ident $( $(($Variant_g:ident))* $ccip_g:ident $clk_doc_g:expr )* ])*
+        $([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $pk_alias:ident $ccip:ident $clk_doc:expr ])*
+        $([ group clk: $pk_g:ident $pk_g_lower:ident $( $(($Variant_g:ident))* $pk_g_alias:ident $ccip_g:ident $clk_doc_g:expr )* ])*
         $([ fixed clk: $clk_doc_f:expr ])*
     ) => {
         paste::item! {
@@ -388,7 +388,7 @@ macro_rules! peripheral_reset_and_enable_control_generator {
                 #[doc=$clk_doc]
                 /// kernel clock source selection
                 pub type [< $pk ClkSel >] =
-                    rcc::[< $ccip >]::[< $pk:upper SEL >];
+                    rcc::[< $ccip >]::[< $pk_alias SEL >];
             )*
             $(          // Group kernel clocks
                 impl [< $pk_g ClkSelGetter >] for $p {}
@@ -398,7 +398,7 @@ macro_rules! peripheral_reset_and_enable_control_generator {
                     #[doc=$clk_doc_g]
                     /// kernel clock source selection.
                     pub type [< $pk_g ClkSel >] =
-                        rcc::[< $ccip_g >]::[< $pk_g:upper SEL >];
+                        rcc::[< $ccip_g >]::[< $pk_g_alias SEL >];
 
                     /// Can return
                     #[doc=$clk_doc_g]
@@ -508,8 +508,8 @@ peripheral_reset_and_enable_control! {
     ];
     #[cfg(feature = "rm0492")]
     AHB2, "" => [
-        Rng [kernel clk: Rng ccipr5 "RNG"],
-        Adc [group clk: AdcDac(Variant) ccipr5 "ADC/DAC"],
+        Rng [kernel clk: Rng RNG ccipr5 "RNG"],
+        Adc [group clk: AdcDac(Variant) ADCDAC ccipr5 "ADC/DAC"],
         Dac12 [group clk: AdcDac]
     ];
 
@@ -522,16 +522,16 @@ peripheral_reset_and_enable_control! {
     ];
     #[cfg(feature = "rm0492")]
     APB1L, "" => [
-        I3c1 [kernel clk: I3c1(Variant) ccipr4 "I3C1"],
+        I3c1 [kernel clk: I3c1(Variant) I3C ccipr4 "I3C1"],
 
-        I2c1 [kernel clk: I2c1 ccipr4 "I2C1"],
-        I2c2 [kernel clk: I2c2 ccipr4 "I2C2"],
+        I2c1 [kernel clk: I2c1 I2C ccipr4 "I2C1"],
+        I2c2 [kernel clk: I2c2 I2C ccipr4 "I2C2"],
 
-        Usart2 [kernel clk: Usart2(Variant) ccipr1 "USART2"],
-        Usart3 [kernel clk: Usart3(Variant) ccipr1 "USART3"],
+        Usart2 [kernel clk: Usart2(Variant) USART ccipr1 "USART2"],
+        Usart3 [kernel clk: Usart3(Variant) USART ccipr1 "USART3"],
 
-        Spi2 [kernel clk: Spi2(Variant) ccipr3 "SPI2"],
-        Spi3 [kernel clk: Spi3(Variant) ccipr3 "SPI3"],
+        Spi2 [kernel clk: Spi2(Variant) SPI123 ccipr3 "SPI2"],
+        Spi3 [kernel clk: Spi3(Variant) SPI123 ccipr3 "SPI3"],
         Opamp,
         Comp
     ];
@@ -542,8 +542,8 @@ peripheral_reset_and_enable_control! {
     ];
     #[cfg(feature = "rm0492")]
     APB1H, "" => [
-        Lptim2 [kernel clk: Lptim2(Variant) ccipr2 "LPTIM2"],
-        Fdcan [kernel clk: Fdcan(Variant) ccipr5 "FDCAN"]
+        Lptim2 [kernel clk: Lptim2(Variant) LPTIM ccipr2 "LPTIM2"],
+        Fdcan [kernel clk: Fdcan(Variant) FDCAN ccipr5 "FDCAN"]
     ];
 
     #[cfg(all())]
@@ -552,9 +552,9 @@ peripheral_reset_and_enable_control! {
     ];
     #[cfg(feature = "rm0492")]
     APB2, "" => [
-        Usb [kernel clk: Usb ccipr4 "USB"],
-        Usart1 [kernel clk: Usart1(Variant) ccipr1 "USART1"],
-        Spi1 [kernel clk: Spi1(Variant) ccipr3 "SPI1"]
+        Usb [kernel clk: Usb USB ccipr4 "USB"],
+        Usart1 [kernel clk: Usart1(Variant) USART ccipr1 "USART1"],
+        Spi1 [kernel clk: Spi1(Variant) SPI123 ccipr3 "SPI1"]
     ];
 
     #[cfg(all())]
@@ -564,9 +564,9 @@ peripheral_reset_and_enable_control! {
     ];
     #[cfg(feature = "rm0492")]
     APB3, "" => [
-        I3c2 [kernel clk: I3c2(Variant) ccipr4 "I3C2"],
-        LpTim1 [kernel clk: LpTim1(Variant) ccipr2 "LPTIM1"],
-        LpUart1 [kernel clk: LpUart1(Variant) ccipr3 "LPUART1"]
+        I3c2 [kernel clk: I3c2(Variant) I3C ccipr4 "I3C2"],
+        LpTim1 [kernel clk: LpTim1(Variant) LPTIM ccipr2 "LPTIM1"],
+        LpUart1 [kernel clk: LpUart1(Variant) USART ccipr3 "LPUART1"]
     ];
 
 }

Original file line number	Diff line number	Diff line change
`@@ -142,7 +142,7 @@ where`
`142`	`142`	`Edge::Rising => exti.rpr1().write(\|w\| w.bits(mask)),`
`143`	`143`	`Edge::Falling => exti.fpr1().write(\|w\| w.bits(mask)),`
`144`	`144`	`_ => panic!("Must choose a rising or falling edge"),`
`145`		`- }`
	`145`	`+ };`
`146`	`146`	`}`
`147`	`147`	`}`
`148`	`148`