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nandojvenandojve
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same70: patch: Fix QDEC deprecated symbols
Keep old symbols for compatibility and easy reading. Signed-off-by: Gerson Fernando Budke <[email protected]>
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‎asf/sam/include/same70b/README‎

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Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ License Link:
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https://www.apache.org/licenses/LICENSE-2.0
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Patch List:
42+
* Fix QDEC deprecated symbols.
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* Fix GMAC_SA register name.
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* Fix XDMAC_CHID register name.
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* Fix TC_CHANNEL register name.

‎asf/sam/include/same70b/component/tc.h‎

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Original file line numberDiff line numberDiff line change
@@ -159,6 +159,15 @@ typedef union {
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#define TC_CMR_BURST_XC0 (TC_CMR_BURST_XC0_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC0 is ANDed with the selected clock. Position */
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#define TC_CMR_BURST_XC1 (TC_CMR_BURST_XC1_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC1 is ANDed with the selected clock. Position */
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#define TC_CMR_BURST_XC2 (TC_CMR_BURST_XC2_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC2 is ANDed with the selected clock. Position */
162+
#define TC_CMR_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */
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#define TC_CMR_LDBSTOP_Msk (_U_(0x1) << TC_CMR_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */
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#define TC_CMR_LDBSTOP TC_CMR_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBSTOP_Msk instead */
165+
#define TC_CMR_LDBDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */
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#define TC_CMR_LDBDIS_Msk (_U_(0x1) << TC_CMR_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */
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#define TC_CMR_LDBDIS TC_CMR_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBDIS_Msk instead */
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#define TC_CMR_ETRGEDG_Pos 8 /**< (TC_CMR) External Trigger Edge Selection Position */
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#define TC_CMR_ETRGEDG_Msk (_U_(0x3) << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */
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#define TC_CMR_ETRGEDG(value) (TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))
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#define TC_CMR_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */
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#define TC_CMR_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge */
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#define TC_CMR_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge */
@@ -167,11 +176,52 @@ typedef union {
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#define TC_CMR_ETRGEDG_RISING (TC_CMR_ETRGEDG_RISING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */
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#define TC_CMR_ETRGEDG_FALLING (TC_CMR_ETRGEDG_FALLING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */
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#define TC_CMR_ETRGEDG_EDGE (TC_CMR_ETRGEDG_EDGE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */
179+
#define TC_CMR_ABETRG_Pos 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */
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#define TC_CMR_ABETRG_Msk (_U_(0x1) << TC_CMR_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */
181+
#define TC_CMR_ABETRG TC_CMR_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_ABETRG_Msk instead */
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#define TC_CMR_CPCTRG_Pos 14 /**< (TC_CMR) RC Compare Trigger Enable Position */
183+
#define TC_CMR_CPCTRG_Msk (_U_(0x1) << TC_CMR_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */
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#define TC_CMR_CPCTRG TC_CMR_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CPCTRG_Msk instead */
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#define TC_CMR_WAVE_Pos 15 /**< (TC_CMR) Waveform Mode Position */
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#define TC_CMR_WAVE_Msk (_U_(0x1) << TC_CMR_WAVE_Pos) /**< (TC_CMR) Waveform Mode Mask */
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#define TC_CMR_WAVE TC_CMR_WAVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVE_Msk instead */
173-
#define TC_CMR_MASK _U_(0x803F) /**< \deprecated (TC_CMR) Register MASK (Use TC_CMR_Msk instead) */
174-
#define TC_CMR_Msk _U_(0x803F) /**< (TC_CMR) Register Mask */
188+
#define TC_CMR_LDRA_Pos 16 /**< (TC_CMR) RA Loading Edge Selection Position */
189+
#define TC_CMR_LDRA_Msk (_U_(0x3) << TC_CMR_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */
190+
#define TC_CMR_LDRA(value) (TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))
191+
#define TC_CMR_LDRA_NONE_Val _U_(0x0) /**< (TC_CMR) None */
192+
#define TC_CMR_LDRA_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */
193+
#define TC_CMR_LDRA_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */
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#define TC_CMR_LDRA_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */
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#define TC_CMR_LDRA_NONE (TC_CMR_LDRA_NONE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) None Position */
196+
#define TC_CMR_LDRA_RISING (TC_CMR_LDRA_RISING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */
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#define TC_CMR_LDRA_FALLING (TC_CMR_LDRA_FALLING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */
198+
#define TC_CMR_LDRA_EDGE (TC_CMR_LDRA_EDGE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */
199+
#define TC_CMR_LDRB_Pos 18 /**< (TC_CMR) RB Loading Edge Selection Position */
200+
#define TC_CMR_LDRB_Msk (_U_(0x3) << TC_CMR_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */
201+
#define TC_CMR_LDRB(value) (TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))
202+
#define TC_CMR_LDRB_NONE_Val _U_(0x0) /**< (TC_CMR) None */
203+
#define TC_CMR_LDRB_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */
204+
#define TC_CMR_LDRB_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */
205+
#define TC_CMR_LDRB_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */
206+
#define TC_CMR_LDRB_NONE (TC_CMR_LDRB_NONE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) None Position */
207+
#define TC_CMR_LDRB_RISING (TC_CMR_LDRB_RISING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */
208+
#define TC_CMR_LDRB_FALLING (TC_CMR_LDRB_FALLING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */
209+
#define TC_CMR_LDRB_EDGE (TC_CMR_LDRB_EDGE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */
210+
#define TC_CMR_SBSMPLR_Pos 20 /**< (TC_CMR) Loading Edge Subsampling Ratio Position */
211+
#define TC_CMR_SBSMPLR_Msk (_U_(0x7) << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */
212+
#define TC_CMR_SBSMPLR(value) (TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))
213+
#define TC_CMR_SBSMPLR_ONE_Val _U_(0x0) /**< (TC_CMR) Load a Capture Register each selected edge */
214+
#define TC_CMR_SBSMPLR_HALF_Val _U_(0x1) /**< (TC_CMR) Load a Capture Register every 2 selected edges */
215+
#define TC_CMR_SBSMPLR_FOURTH_Val _U_(0x2) /**< (TC_CMR) Load a Capture Register every 4 selected edges */
216+
#define TC_CMR_SBSMPLR_EIGHTH_Val _U_(0x3) /**< (TC_CMR) Load a Capture Register every 8 selected edges */
217+
#define TC_CMR_SBSMPLR_SIXTEENTH_Val _U_(0x4) /**< (TC_CMR) Load a Capture Register every 16 selected edges */
218+
#define TC_CMR_SBSMPLR_ONE (TC_CMR_SBSMPLR_ONE_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register each selected edge Position */
219+
#define TC_CMR_SBSMPLR_HALF (TC_CMR_SBSMPLR_HALF_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 2 selected edges Position */
220+
#define TC_CMR_SBSMPLR_FOURTH (TC_CMR_SBSMPLR_FOURTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */
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#define TC_CMR_SBSMPLR_EIGHTH (TC_CMR_SBSMPLR_EIGHTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */
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#define TC_CMR_SBSMPLR_SIXTEENTH (TC_CMR_SBSMPLR_SIXTEENTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */
223+
#define TC_CMR_MASK _U_(0x7FC7FF) /**< \deprecated (TC_CMR) Register MASK (Use TC_CMR_Msk instead) */
224+
#define TC_CMR_Msk _U_(0x7FC7FF) /**< (TC_CMR) Register Mask */
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/* CAPTURE mode */
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#define TC_CMR_CAPTURE_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */
@@ -1155,7 +1205,4 @@ typedef struct {
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/** @} end of Timer Counter */
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1158-
#if !(defined(DO_NOT_USE_DEPRECATED_MACROS))
1159-
#include "deprecated/tc.h"
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#endif /* DO_NOT_USE_DEPRECATED_MACROS */
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#endif /* _SAME70_TC_COMPONENT_H_ */

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