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abi-n32The N32 ABI for 64-bit MIPSThe N32 ABI for 64-bit MIPSabi-sfThe software floating point ABI for various architecturesThe software floating point ABI for various architecturesabi-x32The x32 ABI for 64-bit x86The x32 ABI for 64-bit x86arch-aarch6464-bit Arm64-bit Armarch-amdgcnAMD GCN / RDNAAMD GCN / RDNAarch-avr8-bit AVR8-bit AVRarch-mips32-bit MIPS32-bit MIPSarch-mips6464-bit MIPS64-bit MIPSarch-nvptxNVIDIA PTXNVIDIA PTXarch-powerpc32-bit Power ISA32-bit Power ISAarch-powerpc6464-bit Power ISA64-bit Power ISAarch-riscv3232-bit RISC-V32-bit RISC-Varch-riscv6464-bit RISC-V64-bit RISC-Varch-s390x64-bit IBM z/Architecture64-bit IBM z/Architecturearch-sparc32-bit SPARC32-bit SPARCarch-sparc6464-bit SPARC64-bit SPARCarch-wasm32-bit and 64-bit WebAssembly32-bit and 64-bit WebAssemblyarch-x8632-bit x8632-bit x86arch-x86_6464-bit x8664-bit x86arch-xtensaTensilica XtensaTensilica Xtensabackend-llvmThe LLVM backend outputs an LLVM IR Module.The LLVM backend outputs an LLVM IR Module.enhancementSolving this issue will likely involve adding new logic or components to the codebase.Solving this issue will likely involve adding new logic or components to the codebase.os-hurdGNU HurdGNU Hurdos-uefistandard libraryThis issue involves writing Zig code for the standard library.This issue involves writing Zig code for the standard library.zig ccZig as a drop-in C compiler featureZig as a drop-in C compiler feature
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Description
-  Consider switching 
*-uefi-*targets touefiinstead ofwindowsfor LLVM 21+ #21630 - RISC-V Extension Changes coming to LLVM 22 #25013
 -  Send a patch to LLVM adding 
n32andx32triple environments #25649 -  Potentially send a patch to LLVM adding a 
call0triple environment for Xtensa #25650 -  [PowerPC] Change 
halfto use soft promotion rather thanPromoteFloatllvm/llvm-project#152632 -  [AVR] Change 
halfto usesoftPromoteHalfTypellvm/llvm-project#152783 -  [SPARC] Change 
halfto use soft promotion rather thanPromoteFloatllvm/llvm-project#152727 -  [WebAssembly] Change 
halfto use soft promotion rather thanPromoteFloatllvm/llvm-project#152833 - [llvm-objcopy][libObject] Add RISC-V big-endian support llvm/llvm-project#146913
 - Default stack alignment of X86 Hurd to 16 bytes llvm/llvm-project#158454
 - [ELF][LLDB] Add an nvsass triple llvm/llvm-project#159459
 - [Driver][Hurd] Add AArch64 and RISCV64 support llvm/llvm-project#157212
 - [Driver] Enable __float128 support on X86 on Hurd llvm/llvm-project#160045
 - [AArch64] Improve host feature detection. llvm/llvm-project#160410
 - [RISCV] Add basic Mach-O triple support. llvm/llvm-project#141682
 -  [WebAssembly] Support for new target 
wasm32-linux-muslwalillvm/llvm-project#162581 - AMDGPU: Use ELF mangling in data layout llvm/llvm-project#163011
 - [PowerPC] Take ABI into account for data layout llvm/llvm-project#149725
 - Rename wasm32-wasi to wasm32-wasip1. llvm/llvm-project#165345
 - [clang][RISCV] Add big-endian RISC-V target support llvm/llvm-project#165599
 -  
Lines 441 to 444 in feb05a7
// https://github.com/llvm/llvm-project/issues/135283 if (result.cpu.arch.isMIPS() and result.abi.float() == .soft) { result.cpu.features.addFeature(@intFromEnum(Target.mips.Feature.soft_float)); }  -  
Lines 355 to 356 in bb79c85
// .{ .cpu_arch = .xtensa, .os_tag = .freestanding, .abi = .none }, // .{ .cpu_arch = .xtensa, .os_tag = .linux, .abi = .none },  - beb25b0 & 35d2b1e
 - f90548e & e7f1624
 
Previous upgrade: #23176
rlapzmaxmilton and gustavojoaquin
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abi-n32The N32 ABI for 64-bit MIPSThe N32 ABI for 64-bit MIPSabi-sfThe software floating point ABI for various architecturesThe software floating point ABI for various architecturesabi-x32The x32 ABI for 64-bit x86The x32 ABI for 64-bit x86arch-aarch6464-bit Arm64-bit Armarch-amdgcnAMD GCN / RDNAAMD GCN / RDNAarch-avr8-bit AVR8-bit AVRarch-mips32-bit MIPS32-bit MIPSarch-mips6464-bit MIPS64-bit MIPSarch-nvptxNVIDIA PTXNVIDIA PTXarch-powerpc32-bit Power ISA32-bit Power ISAarch-powerpc6464-bit Power ISA64-bit Power ISAarch-riscv3232-bit RISC-V32-bit RISC-Varch-riscv6464-bit RISC-V64-bit RISC-Varch-s390x64-bit IBM z/Architecture64-bit IBM z/Architecturearch-sparc32-bit SPARC32-bit SPARCarch-sparc6464-bit SPARC64-bit SPARCarch-wasm32-bit and 64-bit WebAssembly32-bit and 64-bit WebAssemblyarch-x8632-bit x8632-bit x86arch-x86_6464-bit x8664-bit x86arch-xtensaTensilica XtensaTensilica Xtensabackend-llvmThe LLVM backend outputs an LLVM IR Module.The LLVM backend outputs an LLVM IR Module.enhancementSolving this issue will likely involve adding new logic or components to the codebase.Solving this issue will likely involve adding new logic or components to the codebase.os-hurdGNU HurdGNU Hurdos-uefistandard libraryThis issue involves writing Zig code for the standard library.This issue involves writing Zig code for the standard library.zig ccZig as a drop-in C compiler featureZig as a drop-in C compiler feature