EmbeddedRiscvJtag support for system bus #454
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Description
This change adds an optional system bus sysBus to the EmbeddedRiscvJtag plugin to support 32-bit read+write accesses per RISC-V Debug Specification v1.0.
When enabled using
withSysBus = true, the plugin exposes aDBusSimpleBusconnected to the DebugModule's system bus. Only 32-bit addresses and accesses are supported for now, but this change could be extended for 128, 64, 16, or 8 bit accesses (see referenced SpinalHDL PR)Depends on this SpinalHDL PR
SpinalHDL/SpinalHDL#1768
(DebugModule system bus support)
Motivation and Context
Without system bus support, debug memory accesses must go through the CPU. I noticed this when building Rust firmware for a VexRiscV based system with RTT logging. When running the firmware with probe-rs, the host continuously looks for new logs in a ring buffer in memory. Without system bus support, this causes delays in the firmware's execution during those memory polls--not helpful when you're working on something with real-time requirements!