iio: frequency: hmc7044: External VCO Mode Fixes #3102
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This corrects the implementation of the external VCO functionality for the HMC7044. The existing implementation treated the external VCO mode similar to HMC7043, with CLKIN1 (FIN) being a reference clock for the dividers, bypassing PLL1 and PLL2. This is not the intended functionality of this device mode. With external VCO mode, PLL1 remains active, using the reference inputs as with normal operation. The PLL2 loop is also closed, with CLKIN1 (FIN) being the VCO, rather than the internal VCO. There were several changes required to accomodate this: - The external VCO has wider frequency limits. PLL2 bounds checks are based on the VCO source - CLKIN1 is no longer used as the PLL2 frequency, using the adi,pll2-output-frequency dt property for both nodes - PLL1 and PLL2 must be enabled in both modes - Corrected status reporting when external VCO is enabled - Remove external VCO as a condition for sync configuration Signed-off-by: Brent Kowal <brent.kowal@analog.com>
Adds the adi,pll2-pfd-invert-enable flag to the bindings file. Signed-off-by: Brent Kowal <brent.kowal@analog.com>
Adds the adi,pll2-pfd-invert-enable device tree property to support changing the polarity of the PLL2 PFD. This is useful for utilizing an external VCO for PLL 2 which has an inversion in the loop filter. Signed-off-by: Brent Kowal <brent.kowal@analog.com>
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btogorean,
buha,
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nunojsa
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Feb 5, 2026
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Just some nits. I'm not familiar enough with the part to reason about the change itself but codewise, LGTM
| #define HMC7044_LOW_VCO_MIN_KHZ 2150000 | ||
| #define HMC7044_LOW_VCO_MAX_KHZ 2880000 | ||
| #define HMC7044_HIGH_VCO_MIN_KHZ 2650000 | ||
| #define HMC7044_HIGH_VCO_MAX_KHZ 3200000 |
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Kind of unrelated change. Adds more diff than needed... Ideally cosmetics changes like this should be done in preliminary patches and apply to the complete driver so the style is consistent.
| of_property_read_bool(np, "adi,pll2-pfd-invert-enable"); | ||
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| if (hmc->pll2_pfd_invert_en && !hmc->clkin1_vcoin_en) | ||
| dev_warn(dev, "PLL2 PFD inverted using internal VCO.\n"); |
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Just to make sure. Is this something allowable or should we just return error here?
| return -EINVAL; | ||
| ret = hmc7044_validate_pll2_freq(hmc, pll2_freq); | ||
| if (ret) | ||
| return ret; |
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Again, the above helper could have been added in a preliminary patch. It makes the reviewer life easier
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@danmois, Moving this back to draft so you can add the additional commits we discussed for PLL1 power-down, PLL2 enabled. |
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PR Description
This corrects the implementation of the external VCO functionality for the HMC7044. The existing implementation treated the external VCO mode similar to HMC7043, with CLKIN1 (FIN) being a reference clock for the dividers, bypassing PLL1 and PLL2. This is not the intended functionality of this device mode.
With external VCO mode, PLL1 remains active, using the reference inputs as with normal operation. The PLL2 loop is also closed, with CLKIN1 (FIN) being the VCO, rather than the internal VCO.
There were several changes required to accomodate this:
are based on the VCO source
adi,pll2-output-frequency dt property for both nodes
Additionally, a device tree flag to enable inversion of PLL2 PFD was added to support external VCO loop filters which have an inversion.
Fixes #3061
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