Search results

how to annotations to ltl properties

Status: Open.

#5118 In chipsalliance/chisel;

· doofin opened on Dec 12, 2025

<code>chisel3.cover</code> drops label in FIRRTL emission

bug

Status: Open.

#5114 In chipsalliance/chisel;

· seldridge opened on Dec 9, 2025

Line up poke() and register output changes in .vcd trace

Status: Open.

#5107 In chipsalliance/chisel;

· oharboe opened on Dec 5, 2025

Chisel 8 Tracker

Status: Open.

#5100 In chipsalliance/chisel;

· seldridge opened on Nov 27, 2025

Adding custom information to Chisel for CIRCT Passes

Status: Open.

#5078 In chipsalliance/chisel;

· liuyic00 opened on Nov 24, 2025

[chiselsim] <code>stepUntil</code>, but asserting if it doesn't happen?

Status: Open.

#5077 In chipsalliance/chisel;

· seldridge opened on Nov 22, 2025

Naming plugin support for arguments

Status: Open.

#5061 In chipsalliance/chisel;

· jackkoenig opened on Oct 23, 2025

[Scala3] SouceLine support for VerificationStatement API

Scala 3Changes related to upgrading to Scala 3Changes related to upgrading to Scala 3

Status: Open.

Task

#5049 In chipsalliance/chisel;

· adkian-sifive opened on Oct 7, 2025

Double-boring can lead to FIRRTL with sink on the RHS of a propassign

bug

Status: Open.

#5038 In chipsalliance/chisel;

· fabianschuiki opened on Sep 30, 2025

HierarchicalModuleName does not work with assert

Status: Open.

#5001 In chipsalliance/chisel;

· mtikekar opened on Aug 3, 2025

<code>stop(msg)</code> does not emit correct verilog

Status: Open.

#4996 In chipsalliance/chisel;

· mtikekar opened on Jul 30, 2025

Allow zero length VecInit()

Status: Open.

#4986 In chipsalliance/chisel;

· oharboe opened on Jul 22, 2025