assist: gen_domain_dts: Add support for PS + PL MB-v zephyr dt genera…#717
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Hi @kedareswararao , Please review this |
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I have a followup PR : #720 |
lopper/assists/gen_domain_dts.py
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| if uart_node.propval('reg') == ['']: | ||
| return | ||
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| reg_value = uart_node.propval('reg', list) |
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Uart node reg value on PS is typicall like eg = <0 0xf1920000 0 0x1000>; this which means you are reading 0 right?
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You’re right – with reg = <0 0xf1920000 0 0x1000> I’m effectively reading 0 and that’s only valid for 32‑bit buses. The reason it still works is that the actual accessibility decision mostly relies on the uart_phandle check; the raw reg[0] comparison is only correct when #address-cells = <1>.
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logic should be generic based on the parent address-cells and size-cells here we should be getting the baseaddress.
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Updated the logic as suggested
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…tion - Fix interrupt controller label mismatch (cpu0_intc vs cpu_intc) - Auto-detect and switch to accessible console UART - Preserve PS serial ports when pruning PS nodes for PL domain - Fix memory selection format for Zephyr - Read UART baud rate from hardware instead of hardcoding Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> Signed-off-by: Bingi Dinesh kumar <dineshkumar.bingi@amd.com>
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@zeddii : Changes looks fine to me when you have sometime take a look into it if it looks fine please merge |
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