firtool-1.132.0

What's Changed

• [ConvertToArcs] Allow ops with regions by @fabianschuiki in #8935
• [Synth][AIG] Move AIG dialect under Synth and remove AIG dialect, NFC by @uenoku in #8956
• [Arc] Add ExecuteOp by @fabianschuiki in #8949
• [ImportVerilog] Add support for materializing FixedSizeUnpackedArrayType as UnpackedArrayType. by @Scheremo in #8960
• [Synth] Implement basic canonicalization/folder to mig.maj_inv by @uenoku in #8959
• [Synth] Add support for mig.maj_inv in longest path analysis by @uenoku in #8965
• [Reduce] Various reducer improvements by @fabianschuiki in #8957
• [SV] Include CallInterface by @uenoku in #8966
• [Moore] Add builtin for $urandom by @Scheremo in #8968
• [ESI] Bump zlib tag by @mortbopet in #8963
• [ESI] Factor out inner execution in Simulator::run by @mortbopet in #8964
• [Synth] Add structural hashing pass for AIG/MIG operations by @uenoku in #8962
• [ConvertToArcs] Add llhd.combinational conversion by @fabianschuiki in #8950
• [Verif] handle self-referencing operations by @ollef in #8972
• [ArcToLLVM] Add arc.execute conversion by @fabianschuiki in #8951
• [AIG] feat : and_inv fold by @markram1729 in #8958
• [Moore] Add builtins for simulation time measurements by @Scheremo in #8970
• [ImportVerilog][Moore] Add support for %t format specifier, introduce moore.fmt.time by @Scheremo in #8979
• [FIRRTL] Emit fopen calls to get fd's not mcd's. by @dtzSiFive in #8981
• [FIRRTL] Add reduction that moves MustDedup onto children by @fabianschuiki in #8969
• [Moore] Add support for $random system task by @Scheremo in #8982
• [ESI] Add skid buffer to Cosim_Endpoint_ToHost by @teqdruid in #8983
• [ESI] Set '--output-split' for verilator compilation by @mortbopet in #8978
• [ESI] Librarify ESI cosim classes by @mortbopet in #8953
• [Datapath] Add product of sum partial product operator by @cowardsa in #8980
• [Moore] Add shortreal type, bit <-> real conversions by @Scheremo in #8985
• [ImportVerilog] Fix missing RValue conversion for struct_create by @Scheremo in #8988
• [Synth] Rename FanIn/FanOut StartPoint/EndPoint by @markram1729 in #8976
• [ESI2Phy] Adapt usage of rewriter to upcoming version. by @ingomueller-net in #8989
• [Synth][Strash] Use RegionDCE instead of UnusedOpPruner by @uenoku in #8990
• [Support] Add walkPostOrder and walkInversePostOrder to InstanceGraph by @fabianschuiki in #8974
• [FIRRTL] Handle ClassTypes properly in Dedup by @fabianschuiki in #8975
• [FIRRTL] Various small reduction pattern tweaks by @fabianschuiki in #8984
• [Moore][ImportVerilog] Add moore.fmt.string, support for $sformatf by @Scheremo in #8993
• Bump LLVM to 580860e8b7341783e8e53114f26b9a9659a3a3e1 by @fzi-hielscher in #8995
• [ImportVerilog][Bug] Fix single argument expressions in severity tasks by @Scheremo in #8998
• [LTL][ImportVerilog] Add support for $rose, $stable, $fell by @Scheremo in #8999
• [Synth] LowerWordsToBits: Improve scalability with bit-sensitive constprop by @uenoku in #8997
• [Arc] Add MergeTaps pass by @fzi-hielscher in #9000
• [Reduce] Various reduction tweaks by @fabianschuiki in #9004
• [FIRRTL] Add a missing unrealized conversion cast in LowerClasses by @fabianschuiki in #9005
• [Synth][LongestPathAnalysis] Remove hack for passing top module name through IR attribute by @uenoku in #9006
• [circt-verilog-lsp] Add definition and reference providers by @uenoku in #8280
• [circt-test] accept LoweringOptions to control the generated Verilog by @ollef in #9001
• [HWLegalizeModules] add disallowClockedAssertions lowering flag by @ollef in #9002
• [FIRRTL] Ensure all types and attributes are walkable by @fabianschuiki in #9007
• [build] Update Slang dependency properties before installing by @jmgorius in #9017
• [ESI] Allow single-file additions to SourceFiles by @mortbopet in #9019
• [Sim] Rename FormatLitOp to FormatLiteralOp, NFC by @fzi-hielscher in #9015
• [Datapath] Custom Partial Product Lowering for computing the Square of the input by @cowardsa in #9010
• [circt-verilog-lsp] Add support for package import indexing by @Scheremo in #9023
• [ESI] Route simulator compilation/exec output through callbacks by @mortbopet in #9009
• [Build] Set /utf-8 flag specifically for slang targets by @fzi-hielscher in #9027
• [ExportVerilog] Require $unsigned for outer-most expression in assignment by @uenoku in #9024

New Contributors

• @ollef made their first contribution in #8972
• @markram1729 made their first contribution in #8958
• @ingomueller-net made their first contribution in #8989
• @jmgorius made their first contribution in #9017

Full Changelog: firtool-1.131.0...firtool-1.132.0