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[Hexagon] Remove post-decoding instruction adjustments #156359

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Merged
merged 1 commit into from
Sep 4, 2025
Merged

[Hexagon] Remove post-decoding instruction adjustments #156359

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3 changes: 1 addition & 2 deletions llvm/lib/Target/Hexagon/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,7 @@ tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler
-ignore-non-decodable-operands)
tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
Expand Down
65 changes: 13 additions & 52 deletions llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -173,6 +173,19 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
const MCDisassembler *Decoder);
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const MCDisassembler *Decoder);

static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
MCContext &Ctx = Decoder->getContext();
MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
return DecodeStatus::Success;
}

static DecodeStatus sgp10ConstDecoder(MCInst &MI,
const MCDisassembler *Decoder) {
MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
return DecodeStatus::Success;
}

#include "HexagonDepDecoders.inc"
#include "HexagonGenDisassemblerTables.inc"

Expand Down Expand Up @@ -349,21 +362,6 @@ void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
}
}

static void adjustDuplex(MCInst &MI, MCContext &Context) {
switch (MI.getOpcode()) {
case Hexagon::SA1_setin1:
MI.insert(MI.begin() + 1,
MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
break;
case Hexagon::SA1_dec:
MI.insert(MI.begin() + 2,
MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
break;
default:
break;
}
}

DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
Expand Down Expand Up @@ -468,12 +466,10 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
CurrentExtender = TmpExtender;
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
adjustDuplex(*MILow, getContext());
Result = decodeInstruction(
DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
adjustDuplex(*MIHigh, getContext());
MCOperand OPLow = MCOperand::createInst(MILow);
MCOperand OPHigh = MCOperand::createInst(MIHigh);
MI.addOperand(OPLow);
Expand All @@ -499,41 +495,6 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,

}

switch (MI.getOpcode()) {
case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
case Hexagon::J4_cmpeqn1_f_jumpnv_t:
case Hexagon::J4_cmpeqn1_fp0_jump_nt:
case Hexagon::J4_cmpeqn1_fp0_jump_t:
case Hexagon::J4_cmpeqn1_fp1_jump_nt:
case Hexagon::J4_cmpeqn1_fp1_jump_t:
case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
case Hexagon::J4_cmpeqn1_t_jumpnv_t:
case Hexagon::J4_cmpeqn1_tp0_jump_nt:
case Hexagon::J4_cmpeqn1_tp0_jump_t:
case Hexagon::J4_cmpeqn1_tp1_jump_nt:
case Hexagon::J4_cmpeqn1_tp1_jump_t:
case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
case Hexagon::J4_cmpgtn1_f_jumpnv_t:
case Hexagon::J4_cmpgtn1_fp0_jump_nt:
case Hexagon::J4_cmpgtn1_fp0_jump_t:
case Hexagon::J4_cmpgtn1_fp1_jump_nt:
case Hexagon::J4_cmpgtn1_fp1_jump_t:
case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
case Hexagon::J4_cmpgtn1_t_jumpnv_t:
case Hexagon::J4_cmpgtn1_tp0_jump_nt:
case Hexagon::J4_cmpgtn1_tp0_jump_t:
case Hexagon::J4_cmpgtn1_tp1_jump_nt:
case Hexagon::J4_cmpgtn1_tp1_jump_t:
MI.insert(MI.begin() + 1,
MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
break;
case Hexagon::Y4_crswap10:
MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
break;
default:
break;
}

if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
MCOperand &MCO = MI.getOperand(OpIndex);
Expand Down
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