GlobalISel: Add tiny hot cache in IRTranslator::ValueToVRegInfo (NFC)#157964

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steven-studio wants to merge 11 commits intollvm:mainfrom

steven-studio:gisel-irtranslator-hot-cache

Commits on Sep 10, 2025

[RISCV][TTI] Fix shift VV opcode mapping in getArithmeticInstrCost
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[RISCV][Tests] Add VV shift codegen + cost-model tests
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feat(codegen): add WIP Segment-Tree register allocator skeleton (disabled by default)
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feat(codegen): WIP Segment-Tree RA with lazy tree + coord compression
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[RegAlloc] WIP: prototype segment tree register allocator
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Add LLVM Segment Tree Register Allocator implementation
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[RegAlloc] Add interval-set based register allocator skeleton
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[RegAlloc] Add scaffold for -regalloc=segmenttree (NFC)
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WIP: hot cache work in progress
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Ignore DeepSeekCodeAnalyzer.py to avoid committing API keys
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Commits on Sep 11, 2025

gitignore: exclude llvm-test-suite and linux directories
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