[RISCV] Fix GPRPairNoX0 Disassembly

[lenary]

Both GPRPair and GPRPairNoX0 were using the same decoder before this change, which meant that GPRPairNoX0 would disassemble zeroes to the X0_Pair.

This ensures the NoX0 decoder correctly fails to decode zeroes.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

Changes

Both GPRPair and GPRPairNoX0 were using the same decoder before this change, which meant that GPRPairNoX0 would disassemble zeroes to the X0_Pair.

This ensures the NoX0 decoder correctly fails to decode zeroes.

---

Full diff: https://github.com/llvm/llvm-project/pull/158001.diff

3 Files Affected:

• (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+9)
• (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.td (+2-4)
• (added) llvm/test/MC/Disassembler/RISCV/zclsd-invalid-pair.txt (+12)

diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 89df9d82f8780..da5d6551092c9 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -255,6 +255,15 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
+  if (RegNo == 0)
+    return MCDisassembler::Fail;
+
+  return DecodeGPRPairRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
 static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo,
                                                 uint64_t Address,
                                                 const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index ccb39e8f42916..82e768d7c1d16 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -358,8 +358,7 @@ let RegAltNameIndices = [ABIRegAltName] in {
   }
 }
 
-let RegInfos = XLenPairRI, CopyCost = 2,
-    DecoderMethod = "DecodeGPRPairRegisterClass" in {
+let RegInfos = XLenPairRI, CopyCost = 2 in {
 def GPRPair : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
     X10_X11, X12_X13, X14_X15, X16_X17,
     X6_X7,
@@ -370,12 +369,11 @@ def GPRPair : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
 )>;
 
 def GPRPairNoX0 : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (sub GPRPair, X0_Pair)>;
-} // let RegInfos = XLenPairRI, DecoderMethod = "DecodeGPRPairRegisterClass"
 
-let RegInfos = XLenPairRI, CopyCost = 2 in
 def GPRPairC : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
   X10_X11, X12_X13, X14_X15, X8_X9
 )>;
+} // let RegInfos = XLenPairRI, CopyCost = 2
 
 //===----------------------------------------------------------------------===//
 // Floating Point registers
diff --git a/llvm/test/MC/Disassembler/RISCV/zclsd-invalid-pair.txt b/llvm/test/MC/Disassembler/RISCV/zclsd-invalid-pair.txt
new file mode 100644
index 0000000000000..7f666ffdfa259
--- /dev/null
+++ b/llvm/test/MC/Disassembler/RISCV/zclsd-invalid-pair.txt
@@ -0,0 +1,12 @@
+# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+zclsd -M no-aliases %s \
+# RUN:   | FileCheck -check-prefixes=CHECK %s
+
+
+[0x00,0x00]
+# CHECK: unimp
+
+[0x52,0x70]
+# CHECK-NOT: c.ldsp zero, {{[0-9]+}}(sp)
+
+[0x00,0x00]
+# CHECK: unimp

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[topperc]

LGTM