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Merge tag 'rolling-lts/hcl-main/6.12.52.4' into project/hcl-dev/6.12 #112

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Merged
hargar19 merged 16 commits into from
Dec 16, 2025
Merged

Merge tag 'rolling-lts/hcl-main/6.12.52.4' into project/hcl-dev/6.12 #112

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5469764
mshv_vtl/tdx: Add member to tdx vp context for TDX timer service
yamahata Oct 13, 2025
c79ca81
mshv_vtl/tdx: Factor out tdg_vp_wr() wrapper
yamahata Oct 13, 2025
1bf0706
mshv_vtl/tdx: Set TSC deadline if userspace requests
yamahata Oct 13, 2025
5992af2
mshv_vtl/tdx: Skip duplicated TDG.VP.WR(TSC deadline)
yamahata Nov 21, 2025
fc1601f
mshv_vtl/tdx: Arm per-cpu timer to wake up from L0 HLT emulation
yamahata Oct 15, 2025
9b80430
mshv_vtl/tdx: Eliminate duplicate tdg.vp.wr(TSC deadline = disarm)
yamahata Nov 20, 2025
3528fd7
drivers: hv: mshv_vtl: Advertise TDX timer service extension
yamahata Oct 20, 2025
8bfc1c1
arch/x86: Unbreak df21bf37518b ("arch/x86: Provide the CPU number in …
yamahata Oct 30, 2025
f526808
Ohcl tdx timer service support
hargar19 Dec 10, 2025
e52cdcd
mshv_vtl/tdx: Fix arm64 build
yamahata Oct 15, 2025
9519a2a
mshv_vtl/tdx: Fix compile error, parameter name omitted
yamahata Dec 10, 2025
5da04eb
mshv_vtl/tdx: Move up one ifdef COFIG_INTEL_TDX_GUEST
yamahata Dec 11, 2025
28e74f6
Add ifdef and define to fix arm64 build
hargar19 Dec 11, 2025
1047cf1
drivers: hv: mshv_vtl: 0 for MSHV_CAP_LOWER_VTL_TIMER_VIRT if unsuppo…
yamahata Dec 11, 2025
97a9e14
drivers: hv: mshv_vtl: return 0 for MSHV_CAP_LOWER_VTL_TIMER_VIRT if …
hargar19 Dec 15, 2025
2672b70
Merge tag 'rolling-lts/hcl-main/6.12.52.4' into project/hcl-dev/6.12
hargar19 Dec 15, 2025
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2 changes: 1 addition & 1 deletion MSFT-Merge/config.json
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
{
"branch": "product/underhill-dev/6.12"
"branch": "product/underhill-main/6.12"
}
2 changes: 1 addition & 1 deletion arch/x86/kernel/apic/apic_numachip.c
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Expand Up @@ -56,7 +56,7 @@ static void numachip2_apic_icr_write(int apicid, unsigned int val)
numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);
}

static int numachip_wakeup_secondary(u32 phys_apicid, unsigned long start_rip)
static int numachip_wakeup_secondary(u32 phys_apicid, unsigned long start_rip, unsigned int cpu)
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Copilot AI Dec 15, 2025

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The parameter cpu is added to the function signature but is not used in the function body. If this parameter is required for API compatibility, consider adding a comment explaining why it's unused, or use the __maybe_unused attribute to document the intentional non-use.

Suggested change
static int numachip_wakeup_secondary(u32 phys_apicid, unsigned long start_rip, unsigned int cpu)
static int numachip_wakeup_secondary(u32 phys_apicid, unsigned long start_rip, unsigned int __maybe_unused cpu)

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{
numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
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18 changes: 17 additions & 1 deletion drivers/hv/mshv_vtl.h
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Expand Up @@ -77,6 +77,21 @@ struct tdx_l2_enter_guest_state {
u8 reserved[6];
};

#define MSHV_VTL_TDX_L2_DEADLINE_DISARMED (0ULL)

/*
* Userspace sets this bit for the kernel to issue TDG.VP.WR(TSC_DEADLINE)
* when it changed deadline.
* The kernel clears this bits on TDG.VP.WR(TSC_DEADLINE).
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Copilot AI Dec 15, 2025

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Grammatical error: 'bits' should be singular 'bit' since only one bit (BIT(0)) is being cleared.

Suggested change
* The kernel clears this bits on TDG.VP.WR(TSC_DEADLINE).
* The kernel clears this bit on TDG.VP.WR(TSC_DEADLINE).

Copilot uses AI. Check for mistakes.
*/
#define MSHV_VTL_TDX_L2_DEADLINE_UPDATE BIT(0)

struct tdx_l2_tsc_deadline {
__u64 deadline;
__u8 update;
__u8 pad[7];
};

/*
* This structure must be placed in a larger structure at offset 272 (0x110).
* The GPR list for TDX and fx_state for xsave have alignment requirements on the
Expand All @@ -91,8 +106,9 @@ struct tdx_vp_context {
__u64 entry_rcx;
/* Must be on 256 byte boundary. */
struct tdx_l2_enter_guest_state l2_enter_guest_state;
struct tdx_l2_tsc_deadline l2_tsc_deadline;
/* Pad space until the next 256 byte boundary. */
__u8 pad3[96];
__u8 pad3[80];
/* Must be 16 byte aligned. */
struct fxregs_state fx_state;
__u8 pad4[16];
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