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@xen0n xen0n commented Oct 29, 2024

Tested on x64, loong64 and riscv64.

Example output on loong64
{
  arch: 'loong64',
  flags: {
    LAM: true,
    UAL: true,
    FPU: true,
    LSX: true,
    LASX: true,
    CRC32: true,
    LVZ: true,
    LBT_X86: true,
    LBT_ARM: true,
    LBT_MIPS: true
  }
}
Example output on riscv64
{
  arch: 'riscv64',
  uarch: '',
  vendor: '',
  flags: { RV64I: true, M: true, A: true, F: true, D: true, C: true, V: true }
}

xen0n added 3 commits October 29, 2024 19:36
Upstream has removed the GYP definitions, so we have to retain it and
sync relevant changes (addition of loong64 and riscv64).

Signed-off-by: WANG Xuerui <[email protected]>
Signed-off-by: WANG Xuerui <[email protected]>
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xen0n commented Oct 29, 2024

Question: I see mips, ppc and x86 are not differentiated for their bitness, but arm and aarch64 are. And aarch64 deviates from the Node arch name arm64. So how do we approach this for the 2 new architectures being added here?

Currently, the cpu_features macros header probes for 64-bit LoongArch only, but the bitness isn't otherwise represented by the cpu_features output, so we must invent a key for that or put the bitness info in arch. RISC-V bitness is deducible from the flags.RVxxI key so I'm not sure if its arch can stay just riscv.

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